參數資料
型號： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強Am486DX系列數據手冊？ 1.87MB（PDF格式）
文件頁數： 15/66頁
文件大小： 1923K
代理商： 20736
Enhanced Am486DX Microprocessor Family
15
P R E L I M I N A R Y
which EADS is active. INV has an internal weak pull-up.
INV is ignored in Write-through mode.
KEN
Cache Enable (Active Low; Input)
KEN determines whether the current cycle is cacheable.
When the microprocessor generates a cacheable cycle
and KEN is active one clock before RDY or BRDY during
the first transfer of the cycle, the cycle becomes a cache
line fill cycle. Returning KEN active one clock before
RDY during the last read in the cache line fill causes the
line to be placed in the on-chip cache. KEN is active
Low and is provided with a small internal pull-up resistor.
KEN must satisfy setup and hold times t
14
and t
15
for
proper operation.
LOCK
Bus Lock (Active Low; Output)
A Low output on this pin indicates that the current bus
cycle is locked. The microprocessor ignores HOLD
when LOCK is asserted (although it does acknowledge
AHOLD and BOFF). LOCK goes active in the first clock
of the first locked bus cycle and goes inactive after the
last clock of the last locked bus cycle. The last locked
cycle ends when RDY is returned. LOCK is active Low
and is not driven during bus hold. Locked read cycles
are not transformed into cache fill cycles if KEN is active.
M/IO
Memory/Input-Output (Active High/Active Low;
Output)
A High output indicates a memory cycle. A Low output
indicates an I/O cycle.
NMI
Non-Maskable Interrupt (Active High; Input)
A High NMI input signal indicates that an external non-
maskable interrupt has occurred. NMI is rising-edge
sensitive. NMI must be held Low for at least four CLK
periods before this rising edge. The NMI input does not
have an internal pull-down resistor. The NMI input is
asynchronous, but must meet setup and hold times t
20
and t
21
for recognition in any specific clock.
PCD
Page Cache Disable (Active High; Output)
This pin reflects the state of the PCD bit in the page
table entry or page directory entry (programmable
through the PCD bit in CR3). If paging is disabled, the
CPU ignores the PCD bit and drives the PCD output
Low. PCD has the same timing as the cycle definition
pins (M/IO, D/C, and W/R). PCD is active High and is
not driven during bus hold. PCD is masked by the Cache
Disable bit (CD) in Control Register 0 (CR0).
PCHK
Parity Status (Active Low; Output)
Parity status is driven on the PCHK pin the clock after
RDY for read operations. The parity status reflects data
sampled at the end of the previous clock. A Low PCHK
indicates a parity error. Parity status is checked only for
enabled bytes as is indicated by the byte enable and
bus size signals. PCHK is valid only in the clock imme-
diately after read data is returned to the microprocessor;
at all other times PCHK is inactive High. PCHK is floated
only during three-state Test mode (see FLUSH).
PLOCK
Pseudo-Lock (Active Low; Output)
In Write-back mode, the processor forces the output
High and the signal is always read as inactive. In Write-
through mode, PLOCK operates normally. When
asserted, PLOCK indicates that the current bus
transaction requires more than one bus cycle. Examples
of such operations are segment table descriptor reads
(8 bytes) and cache line fills (16 bytes). The micropro-
cessor drives PLOCK active until the addresses for the
last bus cycle of the transaction have been driven,
whether or not RDY or BRDY is returned. PLOCK is a
function of the BS8, BS16, and KEN inputs. PLOCK
should be sampled on the clock when RDY is returned.
PLOCK is active Low and is not driven during bus hold.
PWT
Page Write-Through (Active High; Output)
This pin reflects the state of the PWT bit in the page
table entry or page directory entry (programmable
through the PWT bit in CR3). If paging is disabled, the
CPU ignores the PWT bit and drives the PWT output
Low. PWT has the same timing as the cycle definition
pins (M/IO, D/C, and W/R). PWT is active High and is
not driven during bus hold.
RESET
Reset (Active High; Input)
RESET forces the microprocessor to initialize. The mi-
croprocessor cannot begin execution of instructions un-
til at least 1 ms after V
CC
and CLK have reached their
proper DC and AC specifications. To ensure proper mi-
croprocessor operation, the RESET pin should remain
active during this time. RESET is active High. RESET
is asynchronous but must meet setup and hold times
t
20
and t
21
to ensure recognition on any specific clock.
RDY
Non-Burst Ready (Active Low; Input)
A Low input on this pin indicates that the current bus
cycle is complete, that is, either the external system has
presented valid data on the data pins in response to a
read, or the external system has accepted data from the
microprocessor in response to a write. RDY is ignored
when the bus is idle and at the end of the bus cycle’s
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