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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 13/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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Enhanced Am486DX Microprocessor Family
13
P R E L I M I N A R Y
cessor is driving the bus. BREQ is active High and is
floated only during three-state Test mode (see FLUSH).
BS8/BS16
Bus Size 8 (Active Low; Input)/
Bus Size 16 (Active Low; Input)
The BS8 and BS16 signals allow the processor to op-
erate with 8-bit and 16-bit I/O devices by running multiple
bus cycles to respond to data requests: four for 8-bit
devices, and two for 16-bit devices. The bus sizing pins
are sampled every clock. The microprocessor samples
the pins every clock before RDY to determine the ap-
propriate bus size for the requesting device. The signals
are active Low input with internal pull-up resistors, and
must satisfy setup and hold times t
14
and t
15
for correct
operation. Bus sizing is not permitted during copy-back
or write-back operation. BS8 and BS16 are ignored dur-
ing copy-back or write-back cycles.
CACHE
Internal Cacheability (Active Low; Output)
In Write-through mode, this signal always floats. In
Write-back mode for processor-initiated cycles, a Low
output on this pin indicates that the current read cycle
is cacheable, or that the current cycle is a burst write-
back or copy-back cycle. If the CACHE signal is driven
High during a read, the processor will not cache the data
even if the KEN pin signal is asserted. If the processor
determines that the data is cacheable, CACHE goes
active when ADS is asserted and remains in that state
until the next RDY or BRDY is asserted. CACHE floats
in response to a BOFF or HOLD request.
CLK
Clock (Input)
The CLK input provides the basic microprocessor timing
signal. The CLKMUL input selects the multiplier value
used to generate the internal operating frequency for
the Enhanced Am486DX microprocessors. All external
timing parameters are specified with respect to the rising
edge of CLK. The clock signal passes through an inter-
nal Phase-Lock Loop (PLL).
CLKMUL
Clock Multiplier (Input)
The microprocessor samples the CLKMUL input signal
at RESET to determine the design operating frequency.
Table 2 shows the effects CLKMUL has on system con-
figurations for various Enhanced Am486DX micropro-
cessors.
2x indicates that the CPU runs at twice the system bus speed.
3x indicates that the CPU runs at three times the system bus speed.
4x indicates that the CPU runs at four times the system bus speed.
D31
–
D0
Data Lines (Inputs/Outputs)
Lines D31–D0 define the data bus. The signals must
meet setup and hold times t
22
and t
23
for proper read
operations. These pins are driven during the second
and subsequent clocks of write cycles.
D/C
Data/Control (Output)
This bus cycle definition pin distinguishes memory and
I/O data cycles from control cycles. The control cycles
are:
I
Interrupt Acknowledge
I
Halt/Special Cycle
I
Code Read (instruction fetching)
DP3
–
DP0
Data Parity (Inputs/Outputs)
Data parity is generated on all write data cycles with the
same timing as the data driven by the microprocessor.
Even parity information must be driven back into the
microprocessor on the data parity pins with the same
timing as read information to ensure that the processor
uses the correct parity check. The signals read on these
pins do not affect program execution. Input signals must
meet setup and hold times t
22
and t
23
. DP3–DP0 should
be connected to V
CC
through a pull-up resistor in sys-
tems not using parity. DP3–DP0 are active High and are
driven during the second and subsequent clocks of write
cycles.
EADS
External Address Strobe (Active Low; Input)
This signal indicates that a valid external address has
been driven on the address pins A31–A4 of the micro-
processor to be used for a cache snoop. This signal is
recognized while the processor is in hold (HLDA is driv-
en active), while forced off the bus with the BOFF input,
or while AHOLD is asserted. The microprocessor ig-
nores EADS at all other times. EADS is not recognized
if HITM is active, nor during the clock after ADS, nor
during the clock after a valid assertion of EADS. Snoops
to the on-chip cache must be completed before another
snoop cycle is initiated. Table 3 describes EADS when
first sampled. EADS can be asserted every other clock
cycle as long as the hold remains active and HITM re-
Table 2. CLKMUL Settings
Processor
Am486DX2-66
Am486DX4-100
Am486DX5-133
CLKMUL=1
Undefined
3x
Undefined
CLKMUL=0
2x
Undefined
4x
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