參數(shù)資料
型號： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式）
文件頁數(shù)： 17/66頁
文件大?。?/td> 1923K
代理商： 20736
Enhanced Am486DX Microprocessor Family
17
P R E L I M I N A R Y
WB/WT
Write-Back/Write-Through (Input)
If the processor samples WB/WT High at RESET, the
processor is configured in Write-back mode and all sub-
sequent cache line fills sample WB/WT on the same
clock edge in which it finds either RDY or the first BRDY
of a burst transfer to determine if the cache line is des-
ignated as Write-back mode or Write-through. If the sig-
nal is Low on the first BRDY or RDY, the cache line is
write-through. If the signal is High, the cache line is write-
back. If WB/WT is sampled Low at RESET, all cache
line fills are write-through. WB/WT has an internal weak
pull-down.
W/R
Write/Read (Output)
A High output indicates a write cycle. A Low output in-
dicates a read cycle.
Note:
The Enhanced Am486DX microprocessors do
not use the V
CC5
pin used by some 3-V, 486-based
processors. The corresponding pin on the Enhanced
Am486DX microprocessors is an Internal No Connect
(INC).
3
FUNCTIONAL DESCRIPTION
3.1
Overview
The Enhanced Am486DX microprocessors use a 32-bit
architecture with on-chip memory management and
cache memory units. The instruction set includes the
complete 486 microprocessor instruction set along with
extensions to serve the new extended applications. All
applications written for the 486 microprocessor and pre-
vious members of the x86 architectural family can run
on the Enhanced Am486DX microprocessors without
modification.
The on-chip Memory Management Unit (MMU) is com-
pletely compatible with the 486 MMU. The MMU in-
cludes a segmentation unit and a paging unit.
Segmentation allows management of the logical ad-
dress space by providing easy data and code relocati-
bility and efficient sharing of global resources. The
paging mechanism operates beneath segmentation and
is transparent to the segmentation process. Paging is
optional and can be disabled by system software. Each
segment can be divided into one or more 4-Kbyte seg-
ments. To implement a virtual memory system, the En-
hanced Am486DX microprocessors support full
restartability for all page and segment faults.
3.2
Memory is organized into one or more variable length
segments, each up to 4 Gbytes (2
32
bytes). A segment
can have attributes associated with it, including its lo-
cation, size, type (i.e., stack, code, or data), and protec-
tion characteristics. Each task on a microprocessor can
have a maximum of 16,381 segments, each up to
Memory
4 Gbytes. Thus, each task has a maximum of 64 Tbytes
of virtual memory.
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware-enforced
protection allows high-integrity system designs.
3.3
The Enhanced Am486DX microprocessors have four
modes of operation: Real Address mode (Real mode),
Virtual 8086 Address mode (Virtual mode), Protected
Address mode (Protected mode), and System Manage-
ment mode (SMM).
Modes of Operation
3.3.1
In Real mode, the Enhanced Am486DX microproces-
sors operate as a fast 8086. Real mode is required pri-
marily to set up the processor for Protected mode
operation.
Real Mode
3.3.2
In Virtual mode, the processor appears to be in Real
mode, but can use the extended memory accessing of
Protected mode.
Virtual Mode
3.3.3
Protected mode provides access to the sophisticated
memory management paging and privilege capabilities
of the processor.
Protected Mode
3.3.4
SMM is a special operating mode described in detail in
Section 6, beginning on page 38.
System Management Mode
3.4
The Enhanced Am486DX microprocessors support a
superset architecture of the standard 486DX cache im-
plementation. This architectural enhancement improves
not only CPU performance, but total system perfor-
mance.
Cache Architecture
3.4.1
The standard 486DX write-through cache architecture
is characterized by the following:
Write-Through Cache
I
External read accesses are placed in the cache if
they meet proper caching requirements.
I
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
I
Write operations to a valid address in the cache are
updated in the cache andto external memory. This
data writing technique is called write-through.
The write-through cache implementation forces all
writes to flow through to the external bus and back to
main memory. Consequently, the write-through cache
generates a large amount of bus traffic on the external
data bus.
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