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| 型號(hào)： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強(qiáng)Am486DX系列數(shù)據(jù)手冊(cè)？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 21/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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Enhanced Am486DX Microprocessor Family
21
P R E L I M I N A R Y
3.8.2.1
Difference Between Snooping
Access Cases
Snooping accesses are external accesses to the micro-
processor. As described earlier, the snooping logic has
a set of signals independent from the processor-related
signals. Those signals are:
I
EADS
I
INV
I
HITM
In addition to these signals, the address bus is required
as an input. This is achieved by setting AHOLD, HOLD,
or BOFF active.
Snooping can occur in parallel with a processor-initiated
access that has already been started. The two accesses
depend on each other only when a modified line is writ-
ten back. In this case, the snoop requires the use of the
cycle control signals and the data bus. The following
sections describe the scenarios for the HOLD, AHOLD,
and BOFF implementations.
3.8.2.2
The HOLD/HLDA bus arbitration scheme is used prima-
rily in systems where all memory transfers are seen by
the microprocessor. The HOLD/HLDA bus arbitration
scheme permits simple write-back cache design while
maintaining a relatively high performing system. Figure
3 shows a typical system block diagram for HOLD/HLDA
bus arbitration.
HOLD Bus Arbitration Implementation
Note:
To maintain proper system timing, the HOLD
signal must remain active for one clock cycle after HITM
transitions active. Deassertion of HOLD in the same
clock cycle as HITM assertion may ead o unpredictable
processor behavior.
3.8.2.2.1 Processor-Induced Bus Cycles
In the following scenarios, read accesses are assumed
to be cache line fills. The cases also assume that the
core system logic does not return BRDY or RDY until
HITM is sampled. The addition of wait states follows the
standard 486 bus protocol. For demonstration purpos-
es, only the zero wait state approach is shown. Table 7
explains the key to switching waveforms.
3.8.2.2.2 External Read
Scenario:
The data resides in external memory (see
Figure 4).
Step 1 The processor starts the external read access
by asserting ADS = 0 and W/R = 0.
Step 2 WB/WT is sampled in the same cycle as BRDY.
If WB/WT = 1, the data resides in a write-back
cacheable memory location.
Step 3 The processor completes its burst read and as-
serts BLAST.
3.8.2.2.3 External Write
Scenario:
The data is written to the external memory
(see Figure 5).
Step 1 The processor starts the external write access
by asserting ADS = 0 and W/R = 1.
Step 2 The processor completes its write to the core
system logic.
3.8.2.2.4 HOLD/HLDA External Access TIming
In systems with two or more bus masters, each bus
master is equipped with individual HOLD and HLDA con-
trol signals. These signals are then centralized to the
core system logic that controls individual bus masters,
depending on bus request signals and the HITM signal.
CPU
L2 Cache
DRAM
Local Bus
Peripheral
I/O Bus
Interface
Slow
Peripheral
Address Bus
Data Bus
Address Bus
Data Bus
Figure 3. Typical System Block Diagram
for HOLD/HLDA Bus Arbitration
Table 7. Key to Switching Waveforms
Waveform
Inputs
Outputs
Must be steady
Will be steady
May change from
H to L
Will change
from H to L
May change from
L to H
Will change
from L to H
Don’t care; any
change permitted
Changing;
state unknown
Does not apply
Center line is
High-impedance
“Off” state
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