參數(shù)資料
型號： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式）
文件頁數(shù)： 23/66頁
文件大小： 1923K
代理商： 20736
Enhanced Am486DX Microprocessor Family
23
P R E L I M I N A R Y
3.8.3
The following scenarios describe the snooping actions
of an external bus master.
External Bus Master Snooping Actions
3.8.3.1
Scenario
: A snoop of the on-chip cache does not hit a
line, as shown in Figure 6.
Snoop Miss
Step 1 The microprocessor is placed in Snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
Step 2 EADS and INV are applied to the microproces-
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid. Because the addressed line is
not in the snooping cache, HITM is 1.
3.8.3.2
Scenario
: The snoop of the on-chip cache hits a line,
and the line is not modified (see Figure 7).
Snoop Hit to a Non-Modified Line
Step 1 The microprocessor is placed in Snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion.
In the fastest case, this means that HOLD was
asserted one clock cycle before the HLDA re-
sponse.
Step 2 EADS and INV are applied to the microproces-
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid. In this case, HITM is 1.
3.8.4
Scenario
: Write-back accesses are always burst writes
with a length of four 32-bit words. For burst writes, the
burst always starts with the microprocessor line offset
at 0. HOLD must be deasserted before the write-back
can be performed (see Figure 8).
Write-Back Case
Step 1 HOLD places the microprocessor in Snooping
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
Step 2 EADS and INV are asserted. If INV is 0, snoop-
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid, and is 0 because the line is mod-
ified.
HLDA
EADS
HOLD
HITM
ADR
INV
CLK
valid
valid
Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line
Note:
The circled numbers in this figure represent the steps in section 4.8.3.1.
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