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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 32/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
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32
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
Two special bus cycles follow the write-back of modified
data upon execution of the WBINVD instruction: first the
write-back, and then the flush special bus cycle. The
INVD operates identically to the standard 486 micropro-
cessor in that the flush special bus cycle is generated
when the on-chip cache is invalidated. Table 8 specifies
the special bus cycle states for the instructions WBINVD
and INVD.
3.9.2
The other mechanism for cache invalidation is the
FLUSH pin. The FLUSH pin operates similarly to the
WBINVD command, writing back modified cache lines
to main memory. After the entire cache has copied back
all the modified data, the microprocessor generates two
special bus cycles. These special bus cycles signal to
the external caches that the microprocessor on-chip
cache has completed its copy-back and that the second
level cache may begin its copy-back to memory, if so
required.
Cache Invalidation through Hardware
Two flush acknowledge cycles are generated after the
FLUSH pin is asserted and the modified data in the
cache is written back. As with the WBINVD instruction,
in Write-back mode, a flush requires a minimum of 4100
internal clocks to test the cache for modified data. Writ-
ing back modified data adds to this minimum time. The
flush operation can only be stopped by a RESET. Table
9 shows the special flush bus cycle configuration.
3.9.3
As with snooping during normal operation, snooping is
permitted during a cache flush, whether initiated by the
FLUSH pin or WBINVD instruction. After completion of
the snoop, and write-back, if needed, the microproces-
sor completes the copy-back of modified cache lines.
Snooping During Cache Flushing
3.10 Burst Write
The Enhanced Am486DX microprocessors improve
system performance by implementing a burst write fea-
ture for cache line write-backs and copy-backs. Stan-
dard write operations are still supported. Burst writes
are always four 32-bit words and start at the beginning
of a cache line address of 0 for the starting access. The
timing of the BLAST and BRDY signals is identical to
the burst read. Figure 16 shows a burst write access.
(See Figure 17 and Figure 18 for burst read and burst
write access with BOFF asserted.) In addition to using
BLAST, the CACHE signal indicates burstable cycles.
Table 8. WBINVD/INVD Special Bus Cycles
A32–A2
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0000 0000 h
0
0
1
0
1
1
1
Write-back
1
0000 0000 h
0
0
1
1
1
0
1
Flush
1, 2
Notes:
1. WBINVD generates first write-back, then flush.
2. INVD generates only flush.
Table 9. FLUSH Special Bus Cycles
A32–A2
M/IO D/C
W/R BE3 BE2 BE1 BE0
Bus Cycle
0000 0001h
0
0
1
0
1
1
1
First
Flush
Acknowl-
edge
Second
Flush
Acknowl-
edge
0000 0001h
0
0
1
1
1
0
1
BRDY
BLAST
ADS
HITM
EADS
AHOLD
ADR
CLK
n
S
Figure 15. Latest Snooping of Copy-Back
CACHE
Address B
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