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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 1923K |
| 代理商： | 20736 |
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18
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
3.4.2
The microprocessor write-back cache architecture is
characterized by the following:
Write-Back Cache
I
External read accesses are placed in the cache if
they meet proper caching requirements.
I
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
I
Write operations to a valid address in the cache that
is in the write-through (shared) state is updated in
the cache and to external memory.
I
Write operations to a valid address in the cache that
is in the write-back (exclusive or modified) state is
updated onlyin the cache. External memory is not
updated at the time of the cache update.
I
Modified data is written back to external memory
when the modified cache line is being replaced with
a new cache line (copy-back operation) or an exter-
nal bus master has snooped a modified cache line
(write-back).
The write-back cache feature significantly reduces the
amount of bus traffic on the external bus; however, it
also adds complexity to the system design to maintain
memory coherency. The write-back cache requires en-
hanced system support because the cache may contain
data that is not identical to data in main memory at the
same address location.
3.5
The Enhanced Am486DX microprocessor write-back
cache coherency protocol reduces bus activity while
maintaining data coherency in a multimaster environ-
ment. The cache coherency protocol offers the following
advantages:
Write-Back Cache Protocol
I
No unnecessary bus traffic. The protocol dynamical-
ly identifies shared data to the granularity of a cache
line. This dynamic identification ensures that the traf-
fic on the external bus is the minimum necessary to
ensure coherency.
I
Software-transparent. Because the protocol gives
the appearance of a single, unified memory, soft-
ware does not have to maintain coherency or identify
shared data. Application software developed for a
system without a cache can run without modification.
Software support is required only in the operating
system to identify non-cacheable data regions.
The Enhanced Am486DX microprocessors implement
a modified MESI protocol on systems with write-back
cache support. MESI allows a cache line to exist in four
states: modified, exclusive, shared, and invalid. The En-
hanced Am486DX microprocessors allocate memory in
the cache due to a read miss. Write allocation is not
implemented. To maintain coherency between cache
and main memory, the MESI protocol has the following
characteristics:
I
The system memory is always updated during a
snoop when a modified line is hit.
I
If a modified line is hit by another master during
snooping, the master is forced off the bus and the
snooped cache writes back the modified line to the
system memory. After the snooped cache completes
the write, the forced-off bus master restarts the ac-
cess and reads the modified data from memory.
3.5.1
Cache Line Overview
To implement the Enhanced Am486DX microprocessor
cache-coherency protocol, each tag entry is expanded
to 2 bits: S1 and S0. Each tag entry is associated with
a cache line. Table 4 shows the cache line organization.
Table 4. Cache Line Organization
3.5.2
A cache line can occupy one of four legal states as
indicated by bits S0 and S1. The line states are shown
in Table 5. Each line in the cache is in one of these
states. The state transition is induced either by the pro-
cessor or during snooping from an external bus master.
Line Status and Line State
3.5.2.1
An invalid cache line does not contain valid data for any
external memory location. An invalid line does not par-
ticipate in the cache coherency protocol.
Invalid
3.5.2.2
An exclusive line contains valid data for some external
memory location. The data exactly matches the data in
the external memory location.
Exclusive
3.5.2.3
A shared line contains valid data for an external memory
location, the data is shared by another cache, and the
shared data matches the data in the external memory
exactly; or the cache line is in Write-through mode.
Shared
Data Words (32 Bits)
Address Tag and Status
Address Tag, S1, S0
D0
D1
D2
D3
Table 5. Legal Cache Line States
S1
S0
Line State
0
0
1
1
0
1
0
1
Invalid
Exclusive
Modified
Shared
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