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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 50/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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50
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
6.8.2
The CPU does not unconditionally flush its cache before
entering SMM. Therefore, the designer must ensure
that, for systems using overlaid SMRAM, the cache is
flushed upon SMM entry and SMM exit if caching is
enabled.
Cache Flushes
Note:
A cache flush in a system configured in Write-
back mode requires a minimum of 4100 internal clocks
to test the cache for modified data, whether invoked by
the FLUSH pin input or the WBINVD instruction, and
therefore invokes a performance penalty. There is no
flush penalty for systems configured in Write-through
mode.
If the flush at SMM entry is not done, the first SMM read
could hit in a cache that contains normal memory space
code/data instead of the required SMI handler, and the
handler could not be executed. If the cache is not dis-
abled and is not flushed at SMM exit, the normal read
cycles after SMM may hit in a cache that may contain
SMM code/data instead of the normal system memory
contents.
In Write-through mode, assert the FLUSH signal in re-
sponse to the assertion of SMIACT at SMM entry, and,
if required because the cache is enabled, assert FLUSH
again in response to the deassertion of SMIACT at SMM
exit (see Figure 36 and Figure 37). For systems config-
ured in Write-back mode, assert FLUSH with SMI (see
Figure 38).
Reloading the state registers at the end of SMM restores
cache functionality to its pre-SMM state.
6.8.3
Systems based on the MS-DOS operating system con-
tain a feature that enables the CPU address bit A20 to
be forced to 0. This limits physical memory to a maxi-
mum of 1 Mbyte, and is provided to ensure compatibility
with those programs that relied on the physical address
wraparound functionality of the original IBM PC. The
A20M pin on the Enhanced Am486DX microprocessors
provide this function. When A20M is active, all external
bus cycles drive A20 Low, and all internal cache access-
es are performed with A20 Low.
A20M Pin
The A20M pin is recognized while the CPU is in SMM.
The functionality of the A20M input must be recognized
in two instances:
1.
If the SMI handler needs to access system memory
space above 1 Mbyte (for example, when saving mem-
ory to disk for a 0-V suspend), the A20M pin must be
deasserted before the memory above 1 Mbyte is ad-
dressed.
If SMRAM has been relocated to address space above
1 Mbyte, and A20M is active upon entering SMM, the
CPU attempts to access SMRAM at the relocated ad-
dress, but with A20 Low. This could cause the system
2.
to crash, because there would be no valid SMM inter-
rupt handler at the accessed location.
To account for these two situations, the system designer
must ensure that A20M is deasserted on entry to SMM.
A20M must be driven inactive before the first cycle of
the SMM state save, and must be returned to its original
level after the last cycle of the SMM state restore. This
can be done by blocking the assertion of A20M when
SMIACT is active.
6.8.4
The system designer should take into account the fol-
lowing restrictions while implementing the CPU Reset
logic:
CPU Reset During SMM
1.
When running software written for the 80286 CPU,
a CPU RESET switches the CPU from Protected
mode to Real mode. RESET and SRESET have a
higher priority than SMI. When the CPU is in SMM,
the SRESET to the CPU during SMM should be
blocked until the CPU exits SMM. SRESET must
be blocked beginning from the time when SMI is
driven active. Care should be taken not to block the
global system RESET, which may be necessary to
recover from a system crash.
During execution of the RSM instruction to exit
SMM, there is a small time window between the
deassertion of SMIACT and the completion of the
RSM microcode. If a Protected mode to Real mode
SRESET is asserted during this window, it is
possible that the SMRAM space will be violated.
The system designer must guarantee that SRESET
is blocked until at least 20 CPU clock cycles after
SMIACT has been driven inactive or until the start
of a bus cycle.
Any request for a CPU RESET for the purpose of
switching the CPU from Protected mode to Real
mode must be acknowledged after the CPU has
exited SMM. To maintain software transparency,
the system logic must latch any SRESET signals
that are blocked during SMM.
For these reasons, the SRESET signal should be used
for any soft resets, and the RESET signal should be
used for all
hard resets.
2.
3.
6.8.5
Before the processor enters SMM, it empties its internal
write buffers. This is to ensure that the data in the write
buffers is written to normal memory space, not SMM
space. When the CPU is ready to begin writing an SMM
state save to SMRAM, it asserts SMIACT. SMIACT may
be driven active by the CPU before the system memory
controller has had an opportunity to empty the second
level write buffers.
SMM and Second-Level Write Buffers
To prevent the data from these second level write buffers
from being written to the wrong location, the system
memory controller needs to direct the memory write cy-
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