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| 型號： | 20736 |
| 英文描述： | Enhanced Am486DX Family Data Sheet? 1.87MB (PDF) |
| 中文描述： | 增強Am486DX系列數(shù)據(jù)手冊？ 1.87MB（PDF格式） |
| 文件頁數(shù)： | 12/66頁 |
| 文件大小： | 1923K |
| 代理商： | 20736 |
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12
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
2
The Enhanced Am486DX microprocessors provide the
complete interface support offered by the Enhanced
Am486 family. However, the CLKMUL pin settings have
changed to accommodate the higher operating speed
selection. For more information on how all Am486 pro-
cessors differ, see section 8 on page 54.
PIN DESCRIPTION
A20M
Address Bit 20 Mask (Active Low; Input)
A Low signal on the A20M pin causes the microproces-
sor to mask address line A20 before performing a lookup
to the internal cache, or driving a memory cycle on the
bus. Asserting A20M causes the processor to wrap the
address at 1 Mbyte, emulating Real mode operation.
The signal is asynchronous, but must meet setup and
hold times t
20
and t
21
for recognition during a specific
clock. During normal operation, A20M should be sam-
pled High at the falling edge of RESET.
A31–A4/A3–A2
Address Lines (Inputs/Outputs)/(Outputs)
Pins A31–A2 define a physical area in memory or indi-
cate an input/output (I/O) device. Address lines A31–A4
drive addresses into the microprocessor to perform
cache line invalidations. Input signals must meet setup
and hold times t
22
and t
23
. A31–A2 are not driven during
bus or address hold.
ADS
Address Status (Active Low; Output)
A Low output from this pin indicates that a valid bus
cycle definition and address are available on the cycle
definition lines and address bus. ADS is driven active by
the same clock as the addresses. ADS is active Low and is
not driven during bus hold.
AHOLD
Address Hold (Active High; Input)
The external system may assert AHOLD to perform a
cache snoop. In response to the assertion of AHOLD,
the microprocessor stops driving the address bus A31–
A2 in the next clock. The data bus remains active and
data can be transferred for previously issued read or
write bus cycles during address hold. AHOLD is recog-
nized even during RESET and LOCK. The earliest that
AHOLD can be deasserted is two clock cycles after
EADS is asserted to start a cache snoop. If HITM is
activated due to a cache snoop, the microprocessor
completes the current bus activity and then asserts ADS
and drives the address bus while AHOLD is active. This
starts the write-back of the modified line that was the
target of the snoop.
BE3
–
BE0
Byte Enable (Active Low; Outputs)
The byte enable pins indicate which bytes are enabled
and active during read or write cycles. During the first
cache fill cycle, however, an external system should
ignore these signals and assume that all bytes are
active.
I
BE3
for D31–D24
I
BE2 for D23–D16
I
BE1 for D15–D8
I
BE0 for D7–D0
BE3–BE0 are active Low and are not driven during bus
hold.
BLAST
Burst Last (Active Low; Output)
Burst Last goes Low to tell the CPU that the next BRDY
signal completes the burst bus cycle. BLAST is active
for both burst and non-burst cycles. BLAST is active
Low and is not driven during a bus hold.
BOFF
Back Off (Active Low; Input)
This input signal forces the microprocessor to float all
pins normally floated during hold, but HLDA is not as-
serted in response to BOFF. BOFF has higher priority
than RDY or BRDY; if both are returned in the same
clock, BOFF takes effect. The microprocessor remains
in bus hold until BOFF goes High. If a bus cycle is in
progress when BOFF is asserted, the cycle restarts.
BOFF must meet setup and hold times t
18
and t
19
for
proper operation. BOFF has an internal weak pull-up.
BRDY
Burst Ready Input (Active Low; Input)
The BRDY signal performs the same function during a
burst cycle that RDY performs during a non-burst cycle.
BRDY indicates that the external system has presented
valid data in response to a read, or that the external
system has accepted data in response to a write. BRDY
is ignored when the bus is idle and at the end of the first
clock in a bus cycle. BRDY is sampled in the second
and subsequent clocks of a burst cycle. The data pre-
sented on the data bus is strobed into the microproces-
sor when BRDY is sampled active. If RDY is returned
simultaneously with BRDY, BRDY is ignored and the
cycle is converted to a non-burst cycle. BRDY is active
Low and has a small pull-up resistor, and must satisfy
the setup and hold times t
16
and t
17
.
BREQ
Internal Cycle Pending (Active High; Output)
BREQ indicates that the microprocessor has generated
a bus request internally, whether or not the micropro-
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