參數(shù)資料
型號(hào)： 20736
英文描述： Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述： 增強(qiáng)Am486DX系列數(shù)據(jù)手冊(cè)？ 1.87MB（PDF格式）
文件頁(yè)數(shù)： 46/66頁(yè)
文件大?。?/td> 1923K
代理商： 20736
46
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
6.7.4
The I/O instruction restart slot (register offset 7F00h in
SMRAM) gives the SMI handler the option of causing
the RSM instruction to automatically re-execute the in-
terrupted I/O instruction (see Figure 29).
I/O Trap Restart
When the RSM instruction is executed—if the I/O in-
struction restart slot contains the value 0FFh—the CPU
automatically re-executes the l/O instruction that the
SMI signal trapped. If the I/O instruction restart slot con-
tains the value 00h when the RSM instruction is execut-
ed, then the CPU does not re-execute the I/O instruction.
The CPU automatically initializes the I/O instruction re-
start slot to 00h during SMM entry. The I/O instruction
restart slot should be written only when the processor
has generated an SMI on an I/O instruction boundary.
Processor operation is unpredictable when the I/O in-
struction restart slot is set when the processor is servic-
ing an SMI that originated on a non-I/O instruction
boundary.
If the system executes back-to-back SMI requests, the
second SMI handler must not set the I/O instruction re-
start slot. The second back-to-back SMI signal will not
have the I/O Trap Word set.
6.7.5
The I/O Trap Word contains the address of the I/O ac-
cess that forced the external chipset to assert SMI,
whether it was a read or write access, and whether the
instruction that caused the access to the I/O address
was a valid I/O instruction. Table 17 shows the layout.
I/O Trap Word
Bits 31–16 contain the I/O address that was being ac-
cessed at the time SMI became active. Bits 15–2 are
reserved.
If the instruction that caused the I/O trap to occur was
a valid I/O instruction (IN, OUT, INS, OUTS, REP INS,
or REP OUTS), the Valid I/O Instruction bit is set. If it
was not a valid I/O instruction, the bit is saved as a 0.
For REP instructions, the external chip set should return
a valid SMI within the first access.
Bit 0 indicates whether the opcode that was accessing
the I/O location was performing either a read (1) or a
write (0) operation as indicated by the R/W bit.
If an SMI occurs and it does not trap an I/O instruction,
the contents of the I/O address and R/W bit are unpre-
dictable and should not be used.
6.7.6
The Enhanced Am486DX microprocessors provide a
new control register, SMBASE. The SMRAM address
space can be modified by changing the SMBASE reg-
ister before exiting an SMI handler routine. SMBASE
can be changed to any 32K-aligned value. (Values that
are not 32K-aligned cause the CPU to enter the shut-
down state when executing the RSM instruction.) SM-
BASE is set to the default value of 30000h on RESET.
If SMBASE is changed by an SMI handler, all subse-
quent SMI requests initiate a state save at the new SM-
BASE.
SMM Base Relocation
The SMBASE slot in the SMM state save area indicates
and changes the SMI jump vector location and SMRAM
save area. When bit 17 of the SMM Revision Identifier
is set, then this feature exists and the SMRAM base and
consequently, the jump vector, are as indicated by the
SMM Base slot (see Figure 30). During the execution
of the RSM instruction, the CPU reads this slot and ini-
tializes the CPU to use the new SMBASE during the
next SMI. During an SMI, the CPU does its context save
to the new SMRAM area pointed to by the SMBASE,
stores the current SMBASE in the SMM Base slot (offset
7EF8h), and then starts execution of the new jump vec-
tor based on the current SMBASE (see Figure 31).
Table 16. HALT Auto Restart Configuration
Value at
Entry
Value
at Exit
Processor Action on Exit
0
0
Returns to next instruction in interrupt-
ed program
0
1
Unpredictable
1
0
Returns to instruction after HALT
1
1
Returns to interrupted HALT instruction
15
0
I/O instruction restart slot
Register offset 7F00h
Figure 29. I/O Instruction Restart Register Offset
Table 17. I/O Trap Word Configuration
31–16
15–2
1
0
I/O Address
Reserved
Valid I/O Instruction
R/W
Figure 30. SMM Base Slot Offset
31
0
SMM Base
Register Offset 7EF8h
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