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參數(shù)資料
| 型號(hào)： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 13/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
19
Table 3: GT-48001A DRAM Address Mapping
5.1
Receive Buffer Threshold Programming
The number of receive buffers allocated to each port of the GT-48001A is controlled by the RxBufThr field in the Rx
Buffer Threshold register and the DisBufThr* pin. The default value is 29 buffers per port for 1MB DRAM and 79 buffers
per port for 2MB DRAM. If the buffer threshold is disabled (by clearing the BufThrEn bit in the Global Control register or
the DisBufThr* pin is held LOW) the GT-48001A dynamically allocates the buffers to the 8 ethernet ports and the PCI
bus port. In other words, there are no limits on each buffers’ allocation. The RX Buffer Threshold value can be used to
tune performance during development. See Table 4 for Rx Buffer Threshold settings. If a received packet overflows the
Rx buffer allowance, then that packet will be discarded and the Dropped Packets counter will be incremented.
The overflow of the Rx buffer threshold is also indicated by the “Receive Buffer Full” LED in the Serial and Parallel LED
Interfaces (Rx Buffer Threshold must be enabled).
Table 4: Setting the Rx Buffer Threshold
Mem o ry
D esc ri pti o n
1Mbyt e
2Mbyt e
Rx Buffers
304 Buffers for 1Mbyte
992 Buffers for 2 Mbyte
0x00000 - 0x71fff
0x00000 - 0x171fff
PCI Tx Descriptor
0x77000 - 0x088fff
0x177000 - 0x188fff
PCI Rx Descriptor
0x89000 - 0x94fff
0x189000 - 0x194fff
Reserved
4KBytes
0x95000 - 0x095fff
0x195000 - 0x195fff
Tx Descriptor
0x096000 - 0x09ffff
0x196000 - 0x19ffff
Address Table
0xa0000 - 0xfffff
0x1a0000 - 0x1fffff
D i sB uf Thr * P i n
Bu fT h r En Bi t
Re s u lt
HIGH
1
Receive Buffer Size is limited to the
value of RxBufThr
HIGH
0
Dynamic Receive Buffer Allocation
LOW
1
Dynamic Receive Buffer Allocation
LOW
0
Dynamic Receive Buffer Allocation
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