參數(shù)資料
型號(hào): GT-48001A
廠商: Galileo Technology Services, LLC
英文描述: Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器)
中文描述: 交換式以太網(wǎng)控制器10BaseX(10BaseX交換式快速以太網(wǎng)控制器)
文件頁(yè)數(shù): 21/101頁(yè)
文件大?。?/td> 1235K
代理商: GT-48001A
GT-48001A Switched Ethernet Controller
26
Revision 1.6
7.
Device Table Operation
The GalNet Architecture supports a maximum of 32 devices per system. Each device needs to know of the existence of
all other GalNet devices in the system in order to communicate information and packet data. The Device Table is a 32-
bit register that uses a single bit for each possible Device Number to indicate its presence/absence in the system.
7.1
Automatic Device Table Initialization
Upon RESET, each GT-48001A in the system sets all of its Device Table bits to ‘1’. This is essentially a “guess” by the
GT-48001A that
all Device Numbers are in use. In a system with any PCI device that is NOT a GalNet device (CPU,
graphics card, etc.), it recommended that the CPU initialize the device table before the GalNet device is enabled (or
before packet transmission starts).
Specific Device Table bits are cleared, and the corresponding Device Numbers are logically eliminated from the sys-
tem, by:
The receipt of a PCI Master Abort when the GT-48001A attempts to access the corresponding Device Number
Management CPU programming
Device Table “cleaning” is handled automatically by each device upon receipt of the first unknown packet following a
RESET. This process discovers all other GalNet devices in the system without processor intervention:
1.
The GT-48001A receives the first good packet from any Ethernet port and places it in the buffer area in DRAM.
2.
Since the Address Table is cleared (immediately following RESET) the packet must be forwarded to all ports,
including those located on other GalNet devices.
3.
The GT-48001A attempts to allocate a buffer in all 31 possible additional GalNet devices in the system. This is
done by issuing 31 BUFFER_REQUEST messages- one to every possible device in the system.
4.
Each BUFFER_REQUEST message that fails due to a PCI Master Abort results in the corresponding Device Num-
ber bit being cleared in the Device Table. A PCI Master Abort only occurs when there is no target device at the
requested address (i.e. the target device doesn’t exist.)
7.2
Manual Device Table Initialization
Alternatively, the CPU can notify each GT-48001A of the existence of the GalNet devices. This is done by setting the
by setting bit 2 in the global control register (DevTabMod.) In this mode, the CPU is responsible for notifying the GT-
48001A of the existence of all GT-4800x devices in the system. The CPU does this by writing the appropriate values to
each device table.
“Manual” mode must be used when there are multiple PCI buses in the system separated via PCI-to-PCI bridges.
7.3
Programming Device Numbers
The Device Number for each GalNet device is set after RESET by the values on the DAddr[4:0] pins. The device num-
ber can be changed by writing the new device number to [26:22] of the DRAM/Internal Register Base Address Register
at 0x010. Typically, once the number of a device has been changed, the device table of all devices in the system will
also need to be updated.
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