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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網控制器) |
| 中文描述： | 交換式以太網控制器10BaseX（10BaseX交換式快速以太網控制器） |
| 文件頁數(shù)： | 20/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
25
6.6
CRC Generation
As mentioned in Section 6.5, the GT-48001A also includes a CRC generator for packets sent out by the CPU. The
CRC generator enhances system performance by implementing the CPU intensive packet CRC calculation in hard-
ware. Note that CRC generation is not required for packets transferred between GalNet devices, since the CRC is
already appended to these packets.
CRC generation for CPU generated packets is enabled through the EnCRC bit in the Global Control register (bit 29). In
addition, the CPU must set the GenCRC bit in the END_OF_PACKET (Section 10.3.12) message sent to the GT-
48001A at the completion of forwarding the packet.
6.7
Tx Watchdog Timer
The GT-48001A includes a transmit watchdog timer for each transmit queue. The default value of the timer is 630
msec; the range is 105 to 1575 msec in steps of 105 msec. The timer measures the time between the transmission of
two consecutive outgoing packets. When the timer expires, the GT-48001A clears the appropriate used blocks and
sends an interrupt to the CPU via Int*.
The transmit watchdog timer prevents transmission problems on one port from blocking traffic to other ports. In man-
aged systems, the timers also provide a mechanism to notify the CPU of a possible system problem.
The Tx Watchdog Timer can be externally disabled by holding the DisWD* pin LOW. The default is to leave the Tx
Watchdog Timer enabled (DisWD* HIGH.)
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