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參數(shù)資料
| 型號(hào)： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 69/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
7
1.3
Address Recognition
Each GT-48001A in a system can recognize up to 8,000 different Unicast MAC addresses and unlimited Multicast/
Broadcast MAC addresses. An intelligent address recognition mechanism enables filtering and forwarding packets at
full Ethernet wire speed. Hardware assist for address aging and static addresses is also included.
The GT-48001A provides an address self-learning mechanism. Each device has a private address table located in its
DRAM array. As the GT-48001A learns new addresses, it updates all address tables in the system via the GalNet mes-
saging protocol.
1.4
CPU Packet Routing
The GT-48001A has the capability to automatically forward certain packets to the CPU for routing including:
Unicast packets with a destination address tagged for the CPU
Multicast packets
Unknown packets (packets with MAC addresses that have not been recognized)
This gives the system designer the flexibility to decide how to handle such packets in a managed system.
1.5
Intervention Mode
The GT-48001A incorporates an enhanced feature called
intervention mode. This feature permits software or hardware
intervention in the packet routing decision mechanisms for unicast packets. When intervention mode is selected for a
MAC address, the GT-48001A sends the packet to the system CPU instead of switching it as usual. This capability can
be used for many functions including: layer 3 routing, security, virtual LAN support, filtering and management.
1.6
Network Management Features
The GT-48001A provides comprehensive management capabilities enabling the switch OEM to implement a wide
range of network management features. For OEMs offering RMON capability, the GT-48001A provides per-port statis-
tics counters and PCI traffic counters. In addition, the GT-48001A provides station-to-station connectivity matrix infor-
mation and the ability to select a port to work in monitoring (sniffer) mode.
Also included in the GT-48001A is a unique packet sampling capability invented by the Hewlett-Packard Company
called HP-EASE (Embedded Advanced Sampling Environment.) Each port has the ability to take “snapshots” of packet
data at programmable intervals. These samples are forwarded to the management CPU for processing. The samples
can be used to implement HP-EASE compatible messages for OpenView environments, or to create custom manage-
ment information bases such as statistical RMON. Since packets are sampled using this technology, much less local
processing is required over standard RMON implementations. Source addresses of every errored packet are also sent
to the CPU allowing switch OEM to support error counters in RMON host and matrix groups.
Also included in the GT-48001A is hardware assistance for address aging and bridge spanning tree algorithms.
1.7
DRAM Interface
Each GalNet device in the system requires its own, separate EDO DRAM buffer space. The DRAM is used to store the
incoming/outgoing packets as well as the address table and other device data structures. The interface to EDO DRAM
is glueless; all signals needed to control EDO devices are included. For more information, see Section 15.
1.8
PCI Interface
Switch expansion and access to internal management features is possible with the GT-48001A’s PCI interface. The
GT-48001A can be either a master initiating a PCI bus operation or a target responding to a PCI bus operation. Up to
ten GT-48001A devices can reside on the same PCI bus, forwarding packets from one port to the other without CPU
intervention.1 By using PCI-to-PCI bridge devices, the switch can be expanded to up to 32 devices (256 ports).
The PCI bus may also used to connect to an optional CPU for management, or to connect other high speed LAN adapt-
ers such as ATM and FDDI.
1. Ten devices is the physical limit of the PCI specification. Please refer to the PCI bus section of this data sheet for performance limita-
tions.
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