參數(shù)資料
型號(hào)： GT-48001A
廠商： Galileo Technology Services, LLC
英文描述： Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器）
文件頁數(shù)： 87/101頁
文件大小： 1235K
代理商： GT-48001A
GT-48001A Switched Ethernet Controller
86
Revision 1.6
PCI Global Counte rs, Offset: 0x140 040 - 0x140044
The CPU must read all counters during initialization in order to reset the counters to ‘0’. All counters are 32-bits.
21.2
PCI Configuration Registers
The GT- 48001A contains the required PCI configuration registers. These registers are accessed from the PCI.
Device and Vendor ID, PCI Offset: 0x0 (Read Only)
Status and Comma nd, PCI Offset: 0x4
Table 39: PCI MIB Counters
Addr ess
C o u n t e r Na m e
Fun cti o n
In iti a l Va l u e
0x140040
PCIFraRec
Good Frames Received from the PCI
0x0
0x140044
PCIFraSent
Good Frames Sent to the PCI
0x0
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
15:0
VenId
Vendor ID. Provides the manufacturer of the PCI
device. For the GT-48001A this is Galileo’s PCI ven-
dor ID (0x11ab.)
0x11ab
31:16
DevId
Provides the unique GT- 48001A device ID number
0x4801
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
1
MemEn
Memory Enable.
Controls the GT-48001A’s response to memory
accesses.
0 - Disable, the GT-48001A will ignore all memory
accesses on the PCI bus.
1 - Enable, the GT-48001A will respond to memory
accesses on the PCI bus.
0x1
2
MasEn
Master Enable.
Controls the GT-48001A’s ability to act as a master on
the PCI bus.
0 - Disable
1 - Enable
0x1
4
MemWrInv
Memory Write and Invalidate.
Controls the GT-48001A’s ability to generate Memory
Write and Invalidate commands on the PCI bus.
0 - Disable
1 - Enable
0x0
5
Reserved
Reserved.
Read only.
0x0
6
ParEn
Parity Enable.
Controls the GT-48001A’s ability to respond to parity
errors on the PCI.
0 - Disable
1 - Enable
0x0
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