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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網控制器) |
| 中文描述： | 交換式以太網控制器10BaseX（10BaseX交換式快速以太網控制器） |
| 文件頁數(shù)： | 62/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
63
15.
DRAM Interface and Usage
The GT-48001A includes direct support for EDO DRAMs. The performance of EDO satisfies the required bandwidth for
data transfer, address recognition and Tx descriptor fetch/update. The DRAM interface is entirely glueless. All
accesses are performed as 32-bits. The DRAM interface is designed for 60ns EDO DRAMs and all timings are guaran-
teed to work with these devices. Refresh is performed automatically by the GT-48001A. Please refer to the Galileo-6Q
evaluation platform schematics for an example of EDO DRAM design with the GT-48001A.
The GT-48001A requires about 300Kbytes of the DRAM for the address table and other private data structures. The
remainder is used for packet buffers. Following power-up or system RESET, the GT-48001A device creates the MAC
Address Table in DRAM, and initializes all locations in the table to indicate that invalid entries exist in all locations.
Galileo recommends using DRAM with 256K x 16 configuration. When using this configuration, 2 DRAM chips are
required for 1 MByte, and 4 DRAM chips are required for 2 MBytes. If 1 MByte is selected, RAS0* should be con-
nected to 2 DRAM chips while RAS1* should be left unconnected.
If 2 MBytes is selected, RAS0* will control the first 1MB bank, while RAS1* will activate the second 1MB bank.
DData[31:0], DAddr[8:0], CAS*, and WE* should be connected to both banks.
Using 1 or 2 MBytes of DRAM is entirely up to the architect. 2MBytes increases the size of the Rx Buffer space as
shown in Table 3. This performance advantage must be weighed against the cost of additional memory.
16.
LED Support
The GT-48001A supplies a serial bit stream designed to drive status LEDs for each port, as well as for overall system
information. Over 80 internal signals are available through the 3-wire LED port. Galileo also provides reference designs
and example PAL equations in the LED interface application note available on our website.
16.1
Led Indications Interface Description
Table 34 shows the data accessible on the LED Indications Serial Interface for each of the GT-48001A ports.
16.2
LED Serial Interface Description
The LED serial interface consists of three outputs:
LEDClk: LEDClk is the primary timebase of the LED Indications Interface. It is a 50% duty cycle free running
clock at a fixed frequency of 1 MHz. LEDClk is active when Rst* is asserted. LEDClk frequency during Rst* is
10 MHz.
LEDStb: LEDStb (active HIGH) indicates the beginning of the data frame. LEDStb is activated for a duration of
one LEDClk cycle once every 128 LEDClk cycles, starting from Rst* deactivation. This signal marks the begin-
ning of the 128 bit long LED data frame. LEDStb transitions occur 200 ns after LEDClk rising edge.
Table 34: LED Signals Available
D a ta D escr ipt i o n
Sy mbol ic Sig n al N a me
Ty p e
Primary Port Status LED
primary_port_status
n/a
Transmit data in progress
transmit
dynamic
Receive data in progress
receive
dynamic
Collision active
collision
dynamic
Full/Half duplex
full_duplex
static
Receive Buffer Full
rx_buffer_full
dynamic
Forwarding of unknown packets
enabled
unknown_enable
static
The port is configured as Sniffer
port_is_sniffer
static
Link Fail State
link_test_fail
static
Partition State
partition
static
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