參數(shù)資料
型號(hào)： GT-48001A
廠商： Galileo Technology Services, LLC
英文描述： Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 60/101頁(yè)
文件大?。?/td> 1235K
代理商： GT-48001A
GT-48001A Switched Ethernet Controller
Revision 1.6
61
devices (e.g. a broadcast packet), the GT-48001A must provide an indication which allows the CPU to avoid processing
duplicate packets. This indication is provided by the GT-48001A which actually received the packet from an external
link.
An additional bit in the packet header indicates that the sample packet was originally received from an external link to
the CPU as opposed to the PCI system bus. Other GT-48001A devices which sampled the flooded packet only because
it was received from the PCI interface and is being transmitted on a port whose internal counter was decremented to
zero will not have this indication. These samples are “pure” samples and the CPU will know that it should not process
the packet as a normally received packet.
The first word in each 2K block holding the packet to CPU contains the following bits:
Sniffer (bit 31) (active HIGH)
n/a (bits [30:24])
EASE sample for port 7 (bit 23) (active high)
EASE sample for port 6 (bit 22) (active high)
EASE sample for port 5 (bit 21) (active high)
EASE sample for port 4 (bit 20) (active high)
EASE sample for port 3 (bit 19) (active high)
EASE sample for port 2 (bit 18) (active high)
EASE sample for port 1 (bit 17) (active high)
EASE sample for port 0 (bit 16) (active high)
EASE sample is an original packet to CPU (bit 15) (active high)
Source Channel number (bit [14:12], bit 14 is MSB)
Byte Count (bits [11:1], bit 11 is MSB)
Valid bit (bit 0, active HIGH)
These parameters are written at the end of the packet transfer.
14.6
Error Source Indications
EASE software in the network device must keep track of the last receive error sources and the associated error condi-
tions. The GT-48001A informs the CPU of error source conditions by writing the Error_Source message to a new
Error_Source buffer area in CPU memory. Operations in the Error_Source buffer area are similar to those in the
NEW_ADDRESS, START_OF_PACKET and Intervention buffer areas. There is an Error_Source Base Address Reg-
ister in the GT-48001A in which the CPU writes a pointer to the Error_Source buffer area. The Error_Source buffer area
is able to hold 32 entries. Two types of errors are defined for this procedure: FCS error and frames too long. When the
GT-48001A receives a packet with any of the above conditions, it will generate and write an Error_Source message to
the CPU’s buffer area. The Error_Source message will contain the 48-bit source address of the error packet, the source
port number and an indication of the error type. The CPU may poll the Error_Source buffer area for new messages.
However, the GT-48001A includes a separate bit in the Interrupt Cause register which indicates that the GT-48001A has
written an Error_Source message into the CPU’s memory. An appropriate mask bit is defined in the Interrupt Mask reg-
ister.
CPU Error Source Base Address, Offset: 0x 140050
‘Error_Source’: The data written by the GT-48001A device to the ‘Error_Source’ messages buffer area that contains
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
31:8
ErrorSourceBaseAdd
Contains a pointer to the CPU ‘Error_Source’ area. The area
includes 32 entries (2 32-bit words each) for the GT-48001A’s
‘Error_Source’ messages.
0x0
7:0
-
Reserved. Must be 0x0 when written.
-
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