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GT-48001A Switched Ethernet Controller
6
Revision 1.6
1.
Functional Overview
The GT-48001A is a high-performance, low-cost, Switched Ethernet Controller that provides packet switching functions
between eight on-chip 10/20Mbps Ethernet ports and the 1Gbps PCI backplane. The GT-48001A uses the innovative
GalNet Switching Architecture to allow expansion to additional Ethernet, Fast Ethernet and 100VG-AnyLAN ports. The
GT-48001A is backwards compatible with the GT-48001- the industry’s first single-chip Ethernet switch.
1.1
The GalNet Switching Architecture
The GalNet Switching Architecture is based on a proprietary messaging protocol using the industry standard PCI bus
as a medium. GalNet devices are designed to connect seamlessly allowing packets to be switched between devices
without processor intervention (see
Figure 1). Each GalNet device acts as an intelligent agent, sharing information
between all other devices in the system. For example, when one GalNet device learns a new address, it automatically
updates all other GalNet devices via the NEW_ADDRESS message. GalNet messages are defined as
write-only
(request/response) in order to achieve the maximum bandwidth from the PCI bus.
The GalNet Architecture Family currently consists of three products: the GT-48001A (eight ports of 10BaseX), the GT-
48002A (two ports of 100BaseX), and the GT-48003 (two ports of 100VG-AnyLAN). In addition, Galileo Technology
provides a number of other complementary PCI interface products for popular microprocessors.
1.2
Ethernet Ports
The GT-48001A integrates eight Ethernet ports. Each port works at 10Mbps (half-duplex) or 20Mbps (full-duplex) and
includes the Media Access Control (MAC), Manchester encoder/decoder, link integrity logic, auto polarity logic and
LED interface.
The GT-48001A’s Ethernet ports are compliant with both the 802.3 and Ethernet specifications. Physical media such as
10Base-T, 10Base-5, 10Base-2 and 10Base-FL are supported.
Figure 1: Typical 16-port 10-Mbps plus 2-port 100-Mbps Unmanaged Switch Implementation
NOTES:
1) Required PHY circuitry and magnetics not shown
2) PCI bus arbiter is typically implemented in a PAL
3) EDO DRAMs per device are not shown
REQ/GNT PAIR
PCI BUS
GT-48001A
8-Port 10BaseX
Switch
8 10BaseX Ports
GT-48001A
8-Port 10BaseX
Switch
8 10BaseX Ports
GT-48002A
2-Port 100BaseX
Switch
2 100BaseX Ports
PCI BUS
ARBITER
REQ/GNT PAIR