- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67672 > GT-48001A (Galileo Technology Services, LLC) Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 43/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁
GT-48001A Switched Ethernet Controller
46
Revision 1.6
12.
Ethernet Interfaces
The GT-48001A incorporates all the required digital circuitry to interface to 10Base-T, 10Base-5, 10Base-2, 10Base-
FL, and NRZ Synchronous media. Eight Ethernet ports are integrated in the GT-48001A and only a small amount of
external logic is needed to implement the standard physical interfaces.
12.1
Media Access Control (MAC)
The GT-48001A operates in half-duplex or full-duplex modes. In half-duplex mode, the GT-48001A checks that there is
no competitor for the network bus before transmission. In addition to listening for a clear line before transmitting, the
GT-48001A handles collisions in a pre-determined way. If two nodes attempt to transmit at the same time, the signals
collide and the data on the line is garbled. The GT-48001A listens while it is transmitting, and it can detect a collision.
If a collision is detected, the GT-48001A transmits a ‘JAM’ pattern and then delays its re-transmission for a random
time period determined by the backoff algorithm. In full-duplex mode, the GT-48001A transmits unconditionally.
12.2
Illegal Frames
The GT-48001A will discard all illegal frames and increment the appropriate error MIB counters. Examples include:
runts (less than 64 bytes), oversize (greater than 1518 or 1522 bytes), and bad FCS (bad CRC.)
12.3
Selecting the Duplex Mode
Each port can be selected to be in half- or full-duplex mode independently. Following reset the port mode is set by the
state sampled on the TxEn[x] pin. This value can be overridden in each port’s Port Control register.
12.3.0.1 Packet Transmission
If the Col (Collision) signal is not asserted, there is a major difference between Full and Half duplex mode when trans-
mitting packets. In Half duplex mode, the port complies with the "Carrier Sense" part of the CSMA/CD protocol, which
means that a pending transmission will always start only after the programmed interframe gap has expired following
the last of the following two events:
1.
End of receive activity -and-
2.
End of previous transmission
In Full duplex mode, a pending transmission will always start after the programmed interframe gap has expired follow-
ing the end of previous transmission. Any receive activity is ignored.
12.4
Backoff Algorithm Options
The GT-48001A implements the truncated exponential backoff algorithm defined by the 802.3 standard. Aggressive-
ness of the backoff algorithm used by all of the ports is controlled by the Limit4 pin. Limit4 controls the number of con-
secutive packet collisions that will occur before the consequtive collision counter is reset. When Limit4 is LOW, the GT-
48001A resets the collision counter after 16 consecutive retransmit trials, restarts the backoff algorithm, and continues
to try and retransmit the frame. A packet which is endlessly colliding on re-transmits will continue to be re-transmitted
forever, only changing backoff intervals. The GT-48001A supports port partitioning on consecutive collisions, a mode
which must be enabled by the CPU. The retransmission is done from the data already stored in the DRAM. In the case
of a successful transmission, the GT-48001A is ready to transmit any other frames queued in its transmit FIFO within
the minimum IPG of the link.
When Limit4 is HIGH, the GT-48001A will reset its collision counter and restarts the backoff algorithm after 4 consecu-
tive transmit trials. This results in the GT-48001A being more aggressive in acquiring the media following a collision.
This will result in better overall switch throughput (less packet loss) in standardized tests. Limit4 can be toggled during
switch operation.
12.5
Manchester Encoder/Decoder
The Manchester Encoder receives clocked data from the transmit engine and uses an internal 20MHz clock (80MHz
divided by 4) to provide the Manchester-encoded data to the Physical interface. The Manchester Decoder uses the
80MHz clock to recover the receive clock and to sample the incoming data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT-48002A | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器) |
| GT-48004A | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| GT-48006A | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器) |
| GT-48207 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| GT-48208 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT482 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 82pF 3000V SL 5% (12 X 6mm) Radial 9.5mm 85°C |
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。