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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 2/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
10
Revision 1.6
AD[31:0]
I/O
Address/Data: 32-bit multiplexed PCI address and data lines. During the first
clock of the transaction, AD[31:0] contains a physical byte address (32 bits).
During subsequent clock cycles, AD[31:0] contains data.
CBE[3:0]*
I/O
Bus Command/Byte Enable: During the address phase of the PCI transac-
tion, CBE[3:0]* provide the Bus Command. During the data phase, CBE[3:0]*
provide Byte Enables, which determine which bytes carry valid data.
Int*
O
Interrupt Request Line: Int* is asserted by the GT-48001A when one (or
more) of the bits in the Interrupt Cause register is set. This output features an
open-collector driver.
DRAM Interface
DData[31:0]
I/O
DRAM Data: 32-bit EDO DRAM data bus. These signals connect directly to
the data input/output pins of the DRAM devices.
DAddr[8:0]
I/O
DRAM Multiplexed Address Bus: In normal operation, DAddr[8:0] contain
the DRAM multiplexed row/column address. During RESET, these multi-
plexed pins are sampled by the GT-48001A to indicate the Device Number
and the DRAM Parameters (see RESET Configuration section). Values are
determined by connecting pull-up/pull-down resistors. The Device Number and
the DRAM Size are read by the CPU from the Status register.
RAS[1:0]*
O
Row Address Strobes: DRAM row address strobes. RAS[0]* is used for Bank
0. RAS[1]* is used for Bank 1.
CAS*
O
Column Address Strobe: DRAM column address strobe. The GT-48001A
always accesses 32-bit values and does not require a separate CAS* for each
byte.
WE*
O
Write Enable: DRAM write enable.
ChipSel*
O
FIFO Chip Select: ChipSel* asserted by the GT-48001A when a packet’s Des-
tination Port(s), Byte Count, Destination Address and Source Address are read
from the DRAM. This information can be stored in an external FIFO and
accessed by the management CPU for station-to-station connectivity matrix
information.
Ethernet Interfaces
TxEn[7:0]
(Fdx)
I/O
Transmit Enable: TxEn envelopes the transmitted packet.
During reset, this multiplexed input indicates the port mode operation: pull-up
for full duplex, pull-down for half duplex (see RESET Configuration section).
TxD[7:0]
(SerMode0)
I/O
Transmit Data: In normal operation, TxD drives the transmitted data.
During reset, this multiplexed input pin behaves as SerMode0, which together
with TxDDel (SerMode1) indicate the port mode of operation based on pull-up/
pull-down resistors connected to them (see RESET Configuration section).
TxDDel[7:0]
(SerMode1)
I/O
Transmit Data Delayed: In normal operation, TxDDel outputs the transmitted
data delayed. TxDDel follows the TxD signal by 50nsec.
During reset, this multiplexed input pin behaves as SerMode1, which together
with TxD (SerMode0) indicate the port mode of operation based on pull-up/
pull-down resistors connected to them (see RESET Configuration section).
CrS/RxEn[7:0]
I/O
Carrier Sense/Receive Enable: In 10Base-T, 10Base-FL and AUI, this output
pin indicates the Carrier Sense.
In Sync mode, this input pin envelopes the receive packet.
RxD[7:0]
I
Receive Data: RxD is the received serial bitstream from the Ethernet wire.
S y mbol
Ty p e
D esc ri pti o n
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