參數(shù)資料
型號： GT-48001A
廠商： Galileo Technology Services, LLC
英文描述： Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器）
文件頁數(shù)： 49/101頁
文件大?。?/td> 1235K
代理商： GT-48001A
GT-48001A Switched Ethernet Controller
Revision 1.6
51
put as described above, it is probable that after exiting from link-test-fail, the Pol state will not match the actual RxD pair
wiring e.g. the RxD pair is correct but Pol = 0. Since the received packet is inverted internally when Pol = 0, the
received packets will be rejected due to bad CRC. The incoming packets may correct the polarity, thus resolving this
temporary problem, as described below.
When the Auto-Polarity function is enabled, every received packet, which is of valid length (512 data bits or more), and
did not experience a collision, is used to update the internal polarity indication (which is driven externally through Pol
output). This is done by sampling the Start of TP_IDL symbol found at the end of the packet. (Start of TP_IDL is defined
in Fig 14-10 in the 802.3 std). If a positive polarity minimum size packet is received (e.g. a 64 byte packet through cor-
rect RxD pair connection), and Pol = 0, then the Start Frame Delimiter (SFD) which follows the Preamble will not be
detected since the data is internally inverted. It is probable that a bit string matching the SFD pattern will be found as
part of the packet data content, but this packet will be regarded as too short and will not update the polarity state (as
noted earlier). Longer packet are more probable to correct the polarity. Once a packet corrects the polarity to Pol = 1,
any further packets will be received correctly.
12.12.3 10BaseFL Mode
Table 28: 10BaseFL Ethernet Interface Pin Descriptions
Pi n Na m e
I/ O
1 0 Ba seF
Mo de
Fu n c t i on a l it y
SClk
I
80 MHz
80 MHz Clock.
RxD
I
RxD
Receive Data: Manchester encoded data. Link Integrity Test
is performed on this input whenever there is no incoming
packet. The Link Test function monitors the existence of a
valid OPT_IDL (1 MHz periodic pulse). At the absence of the
OPT_IDL, the port will enter Link Test Fail (LTF) state.
RxLP
I
unused
Should be connected to logic HIGH
CrS
O
CrS
Carrier Sense: Indicates presence on received packet (pre-
amble to SOI).
Pol
O
NC
TxD
O
TxD
Transmit Data: Manchester encoded data. Whenever data is
not being transmitted, the idle signal, OPT_IDL, is transmitted
via the TxD. The OPT_IDL is a periodic pulse waveform of fre-
quency 1 MHz. Following a packet and the SOI, the OPT_IDL
starts with a logic HIGH.
TxDDel
O
TxDDel
Transmit Data Delayed: TXD Delayed by 50ns.
TxEn
O
TxEn
Transmit Enable. Always High
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