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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 18/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
23
Figure 3: CPU Memory Data Structure
The data structure components are the following:
CPU Base Address Register (CBA)1 - A register that points to the beginning of a sixteen block area in CPU
memory.
CPU Base Address Shadow Register (CBAS) - A second register that holds a pointer to a second sixteen
block area in the CPU main memory. The value in the Shadow register propagates into the Base Address reg-
ister after sixteen packets are transferred to the main memory.
Buffer Area - The CPU buffer area consists of 16 blocks of 2Kbytes each. The first word (Word #0) of each
block contains the Sniffer Indication [31], EASE indication [23:15], Source Port Number [14:12], Byte Count
(bits [11:1]), and the Valid bit (bit 0). These bits are written as the END_OF_PACKET (Section 10.3.10) mes-
sage transferred from the source GT-48001A to the CPU at the end of a valid packet transfer. Words 1 to 7 are
left empty for user purposes.
The communication between the GT-48001A and the CPU follows this sequence:
1.
Upon initialization, CPU updates the CBA (1st write to 0x140034).
2.
Following the initial write to the CBA, the CPU updates the CBAS (2nd write to 0x140034).
3.
GT-48001A transfers 16 packets to the CPU main memory and asserts the Int* at the end of each packet transfer.
4.
The CPU must count sixteen interrupts and then update the Shadow register in the GT-48001A (write to
0x140034). Also, the BufWrap interrupt can be checked instead of counting sixteen interrupts. In other words, the
CPU must update 0x140034 ONCE after 16 packets have been transferred from the GT-48001A to the CPU. This
single word write after sixteen packets have been transferred to the CPU are to update the Shadow register only.
1. Assuming CBA and CBAS have already been written to, any writes to 0x140034 will update the CBAS register ONLY. In other words,
CBA can only be updated on the first write, and after 16 packets have been written to the CPU where the CBA will take the value of the
CBAS.
Block #1
Block #2
Block #16
0
1
2
3
n-1
n
31
0
Word#8,
BASE ADDRESS
REGISTER
Byte#32
GT-48001A
CPU Memory
BASE ADDRESS
SHADOW
S
31
EASE
23
15
SP
14 12
BC
V
11
1
0
Word#0,
Byte#0
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