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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 91/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
9
2.2
Pin Functions and Assignment
Sy m b ol
Ty p e
De s c ri pti o n
PCI Bus Interface
Rst*
I
RESET: Active LOW. Rst* must be asserted for at least 10 PCI clock cycles.
When in the reset state, all PCI output pins are tristated and all open drain sig-
nals are floated. Following Rst* deassertion, the GT-48001A clears the internal
buffers and initializes the address table in the DRAM. The address table initial-
ization takes 165,000 CLK cycles to complete. Any incoming packets during
the address table initialization, are ignored.
Clk
I
Clock: Provides the timing for the GT-48001A internal units. All functional
units except for the serial interfaces use this clock.Clk also provides timing for
PCI bus transactions. The clock frequency is 30-33MHz.
Req*
O
Bus Request: Asserted by the GT-48001A to indicate to the PCI bus arbiter
that this device requires mastership of the bus.
Gnt*
I
Bus Grant: Indicates to the GT-48001A that access to the PCI bus is granted.
PErr*
I/O
Parity Error: Asserted when a data parity error is detected on the PCI bus.
SErr*
O
System Error: Asserted by the GT-48001A when an address parity error is
detected on the PCI bus. The GT-48001A asserts SErr* two cycles after the
failing address. This output features an open-collector driver.
IDSel
I
Initialization Device Select: Asserted by a PCI bus master to gain access to
the GT-48001A’s configuration header during configuration read/write transac-
tions.
DevSel*
I/O
Device Select: Asserted by the target of the current PCI access. When the
GT-48001A is a bus master, it expects the target to assert DevSel* within 5
bus cycles, confirming the access. If the target does not assert DevSel* within
the required bus cycles, the GT-48001A aborts the cycle. As a target, the GT-
48001A asserts DevSel* as a “medium speed” PCI device (two cycles after
the assertion of Frame*).
Stop*
I/O
Stop: Indicates that the current target is requesting the bus master to stop the
current transaction. As a master, the GT-48001A responds to the assertion of
Stop* by either disconnecting, retrying, or aborting. As a target, the GT-
48001A asserts Stop* to force a retry.
Frame*
I/O
Cycle Frame: Asserted by the GT-48001A to indicate the beginning and dura-
tion of a master transaction. Frame* is asserted to indicate the beginning of the
cycle. While Frame* is asserted, data transfer continues. Frame* is deasserted
to indicate that the next data phase is the final data phase transaction. Frame*
is monitored when the GT-48001A acts as a target, to detect a configuration or
memory transaction.
Par
I/O
Parity: Calculated by the GT-48001A as an even parity bit for the AD[31:0]
and CBE[3:0]* lines.
TRdy*
I/O
Target Ready: Indicates the target agent’s ability to complete the current data
phase of the transaction. A data phase is completed on any clock when both
TRdy* and IRdy* are asserted. Wait cycles are inserted until both IRdy* and
TRdy* are asserted together.
IRdy*
I/O
Initiator Ready: Indicates the bus master’s ability to complete the current data
phase of the transaction. A data phase is completed on any clock when both
TRdy* and IRdy* are asserted. Wait cycles are inserted until both IRdy* and
TRdy* are asserted together.
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