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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 88/101頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
87
Class Code and Revision ID, Offset: 0x 008 (Read-Only)
8
SysErrEn
System Error Enable.
Controls the GT-48001A’s ability to assert the SErr*
pin.
0 - Disable
1 - Enable
0x0
22:9
Reserve
Reserved.
Read only.
0x0
23
TarFastBB
Target Fast Back-to-Back.
This indicates that the GT-48001A is capable of
accepting Fast Back-to-Back transactions on the PCI
bus. Read-only bit.
0x1
24
DataParDet
Data Parity Detected.
This bit is set by the GT-48001A when it detects a
Data Parity Error during a master operation. This bit is
cleared by writing ‘1’ to it.
0x0
26:25
DevSelTim
Device Select Timing.
These bits indicate the GT-48001A‘s DevSel* timing.
The GT-48001A’s DevSel* timing is always set at
medium (01), as defined in the PCI specification.
Read only.
0x1
28
TarAbort
Target Abort.
This bit is set upon Target Abort. This bit is cleared by
writing ‘1’ to it.
0x0
29
MastAbort
Master Abort.
This pin is set upon Master Abort. This bit is cleared
by writing ‘1’ to it.
0x0
30
SysError
System Error.
This pin is set upon System Error. This bit is cleared
by writing ‘1’ to it.
0x0
31
DetParErr
Detected Parity Error.
This pin is set upon detection of Parity Error (in both
master and slave operations). This bit is cleared by
writing ‘1’ to it.
0x0
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
7:0
RevID
Revision ID.
Indicates the GT-48001A revision number.
GT-48001A
0x10
GT-48001
0x00
23:16
SubClass
SubClass.
Indicates the GT-48001A Subclass (0x0 - Ethernet).
0x0
31:24
BaseClass
Base Class.
Indicates the GT-48001A Base Class (0x2 - Network
Device).
0x2
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
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