參數(shù)資料
型號(hào): LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁(yè)數(shù): 18/90頁(yè)
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
18
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 4. LXT971A Miscellaneous Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
1
Signal Description
D1
D2
5
6
TxSLEW0
TxSLEW1
I
Tx Output Slew Controls 0 and 1
. These pins select the TX
output slew rate (rise and fall time) as follows:
TxSLEW1
TxSLEW0
Slew Rate (Rise and Fall Time)
0
0
3.0 ns
0
1
3.4 ns
1
0
3.9 ns
1
1
4.4 ns
C2
4
RESET
I
Reset
. This active Low input is OR’ed with the control
register Reset bit (Register bit 0.15). The LXT971A reset
cycle is extended to 258
μ
s (nominal) after reset is de-
asserted.
G1
F1
F2
E2
E1
16
15
14
13
12
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
I
I
I
I
I
Address <4:0>
. Sets device address.
H1
17
RBIAS
AI
Bias
. This pin provides bias current for the internal circuitry.
Must be tied to ground through a 22.1 k
, 1% resistor.
H8
33
PAUSE
I
Pause
. When set High, the LXT971A advertises Pause
capabilities during auto-negotiation.
H7
32
SLEEP
I
Sleep
. When set High, this pin enables the LXT971A to go
into a low-power sleep mode. The value of this pin can be
overridden by Register bit 16.6 when in managed mode.
E8
39
PWRDWN
I
Power Down
. When set High, this pin puts the LXT971A in a
power-down mode.
B1
C1
1
2
REFCLK/XI
XO
I
O
Crystal Input and Output
. A 25 MHz crystal oscillator circuit
can be connected across XI and XO. A clock can also be
used at XI. Refer to
“Clock Requirements” on page 26
in the
Functional Description section.
B7, C7
D7
9, 10
44
N/C
-
No Connection
.
These pins are not used and should not be
terminated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
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