參數資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網物理層收發(fā)器
文件頁數: 19/90頁
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
19
Table 5. LXT971A Power Supply Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
Signal Description
A6
51
VCCD
Digital Power.
Requires a 3.3V power supply.
D4, E3
E4, F3
F4, C6,
C3, G7,
G8
7, 11, 18,
25, 34,
35, 41,
50, 61
GND
Ground.
E5, D5
8, 40
VCCIO
MII Power.
Requires either a 3.3V or a 2.5V supply. Must
be supplied from the same source used to power the MAC
on the other side of the MII.
G3, G4
21, 22
VCCA
Analog Power.
Requires a 3.3V power supply.
Table 6. LXT971A JTAG Test Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
1
Signal Description
F5
27
TDI
2
I
Test Data Input
. Test data sampled with respect to the
rising edge of TCK.
G5
28
TDO
2
O
Test Data Output
. Test data driven with respect to the
falling edge of TCK.
F6
29
TMS
2
I
Test Mode Select
.
G6
30
TCK
2
I
Test Clock
. Test clock input sourced by ATE.
H6
31
TRST
2
I
Test Reset
. Test reset input sourced by ATE.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.
Table 7. LXT971A LED Signal Descriptions
PBGA
Pin#
LQFP
Pin#
Symbol
Type
1
Signal Description
E6
F7
F8
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
LED Drivers 1-3.
These pins drive LED indicators. Each
LED can display one of several available status
conditions as selected by the LED Configuration Register
(refer to
Table 56 on page 85
for details).
Configuration Inputs 1-3.
These pins also provide initial
configuration settings (refer to
Table 9 on page 30
for
details).
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. Pull-up/pull-down resistors of 10 k can be implemented if LEDs are used in the design.
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