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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 75/90頁 |
| 文件大小： | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
75
Table 44. MII Status Register #1 (Address 1)
Bit
Name
Description
Type
1
Default
1.15
100BASE-T4
Not Supported
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
RO
0
1.14
100BASE-X Full-Duplex
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
RO
1
1.13
100BASE-X Half-Duplex
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
RO
1
1.12
10 Mbps Full-Duplex
1 = PHY able to operate at 10 Mbps in full-duplex
mode
0 = PHY not able to operate at 10 Mbps full-duplex
mode
RO
1
1.11
10 Mbps Half-Duplex
1 = PHY able to operate at 10 Mbps in half-duplex
mode
0 = PHY not able to operate at 10 Mbps in half-
duplex
RO
1
1.10
100BASE-T2 Full-
Duplex
Not Supported
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
RO
0
1.9
100BASE-T2 Half-
Duplex
Not Supported
1 = PHY able to perform half-duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-
T2
RO
0
1.8
Extended Status
1 = Extended status information in register 15
0 = No extended status information in register 15
RO
0
1.7
Reserved
1 = ignore when read
RO
0
1.6
MF Preamble
Suppression
1 = PHY accepts management frames with
preamble suppressed
0 = PHY will not accept management frames with
preamble suppressed
RO
0
1.5
Auto-Negotiation
complete
1 = Auto-negotiation complete
0 = Auto-negotiation not complete
RO
0
1.4
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
RO/LH
0
1.3
Auto-Negotiation Ability
1 = PHY is able to perform auto-negotiation
0 = PHY is not able to perform auto-negotiation
RO
1
1.2
Link Status
1 = Link is up
0 = Link is down
RO/LL
0
1.1
Jabber Detect
1 = Jabber condition detected
0 = Jabber condition not detected
RO/LH
0
1.0
Extended Capability
1 = Extended register capabilities
0 = Basic register capabilities
RO
1
1. RO = Read Only
LL = Latching Low
LH = Latching High
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|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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