參數(shù)資料
型號(hào)： LXT971A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述： 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁(yè)數(shù)： 74/90頁(yè)
文件大?。?/td> 568K
代理商： LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
74
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 43. Control Register (Address 0)
Bit
Name
Description
Type
1
Default
0.15
Reset
1 = PHY reset
0 = Normal operation
R/W
SC
0
0.14
Loopback
1 = Enable loopback mode
0 = Disable loopback mode
R/W
0
0.13
Speed Selection
0.6
0.13
Speed Selected
R/W
Note 2
1
1
0
0
1
0
1
0
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.12
Auto-Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
R/W
Note 2
0.11
Power-Down
1 = Power-down
0 = Normal operation
R/W
0
0.10
Isolate
1 = Electrically isolate PHY from MII
0 = Normal operation
R/W
0
0.9
Restart
Auto-Negotiation
1 = Restart auto-negotiation process
0 = Normal operation
R/W
SC
0
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
R/W
Note 2
0.7
Collision Test
1 = Enable COL signal test
0 = Disable COL signal test
R/W
0
0.6
Speed Selection
0.6
0.13
Speed Selected
R/W
0
1
1
0
0
1
0
1
0
Reserved
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.5:0
Reserved
Write as 0, ignore on Read
R/W
00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFG
n
pins (refer to
Table 9 on
page 30
).
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