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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 42/90頁 |
| 文件大?。?/td> | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
42
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
3.7.3.2.4
Receive Data Valid
The LXT971A asserts RX_DV to indicate that the received data maps to valid symbols. However,
RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and de-
scrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as
well as receiving, polarity correction, and baseline wander correction functions.
Scrambler/De-scrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
Scrambler Seeding
Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce
EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are
determined by the PHY address, and the remaining bits are hard coded in the design.
Scrambler Bypass
The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is
automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic
and test support.
3.7.3.3.1
Baseline Wander Correction
The LXT971A provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by
definition “unbalanced”. This means that the average value of the signal voltage can “wander”
significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at
long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are
completely data dependent.
The LXT971A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over all cable lengths.
3.7.3.3.2
Polarity Correction
The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the
receive signal at TPFIP and TPFIN is inverted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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