參數(shù)資料
型號(hào)： LXT971A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述： 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁(yè)數(shù)： 8/90頁(yè)
文件大?。?/td> 568K
代理商： LXT971A
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
8
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Revision History
Revision 002
Revision Date: August 6, 2002
Page
Description
Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V.
1
Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL).
Added “JTAG Boundary Scan” to Product Features on front page.
12
Modified
Figure 2 “LXT971A 64-Ball PBGA Assignments”
(replaced TEST1 and TEST0 with GND).
13
Modified
Figure 3 “LXT971A 64-Pin LQFP Assignments”
(replaced TEST1 and TEST0 with GND).
14
Modified
Table 1 “LQFP Numeric Pin List”
(replaced TEST1 and TEST0 with GND).
16
Added note under
Section 2.0, “Signal Descriptions”
: “Intel recommends that all inputs and multi-
function pins be tied to the inactive states and all outputs be left floating, if unused.”
17
Modified SD/TP description in
Table 3 “LXT971A Network Interface Signal Descriptions”
.
Added Table note 2.
18
Modified
Table 4 “LXT971A Miscellaneous Signal Descriptions”
.
19
Modified
Table 5 “LXT971A Power Supply Signal Descriptions”
.
20
Added
Table 8 “LXT971A Pin Types and Modes”
.
22
Replaced second paragraph under
Section 3.2.1.2, “Fiber Interface”
.
23
Added
Section 3.2.2.1, “Increased MII Drive Strength”
.
23
Changed “Far-End Fault” title to
‘100BASE-FX Far-End Fault”
.
Modified first sentence under this heading.
30
Modified
Figure 8 “Hardware Configuration Settings”
.
35
Added paragraph after bullets under
Section 3.6.7.2, “Test Loopback”
.
43
Modified text under
Section 3.7.3.4, “Fiber PMD Sublayer”
.
47
Modified
Table 13 “Supported JTAG Instructions”
.
47
Modified
Table 14 “Device ID Register”
.
52
Added a new
Section 4.3, “The Fiber Interface”
.
53
Replaced
Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry”
.
54
Added
Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry”
.
55
Added
Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Translator”
.
56
Modified
Table 17 “Absolute Maximum Ratings”
.
56
Modified
Table 18 “Operating Conditions”
: Added Typ values to Vcc current.
57
Modified
Table 20 “Digital I/O Characteristics - MII Pins”
.
58
Modified
Table 22 “I/O Characteristics - LED/CFG Pins”
.
58
Added
Table 23 “I/O Characteristics – SD/TP Pin”
.
60
Added
Table 28 “LXT971A Thermal Characteristics”
.
65
Modified
Table 33 “10BASE-T Receive Timing Parameters”
72
Modified
Table 42 “Register Bit Map”
. (Added Table 26 information).
86
Added
Table 57 “Digital Config Register (Address 26)”
.
87
Modified
Table 58 “Transmit Control Register (Address 30)”
.
90
Added
Section 8.0, “Product Ordering Information”
.
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