參數(shù)資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁數(shù): 84/90頁
文件大小: 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
84
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 55. Interrupt Status Register (Address 19, Hex 13)
Bit
Name
Description
Type
1
Default
19.15:9
Reserved
Ignore
RO
N/A
19.8
Reserved
Ignore
RO
0
19.7
ANDONE
Auto-negotiation Status
1= Auto-negotiation has completed.
0= Auto-negotiation has not completed.
RO/SC
N/A
19.6
SPEEDCHG
Speed Change Status
1 = A Speed Change has occurred since last reading
this register.
0 = A Speed Change has not occurred since last
reading this register.
RO/SC
0
19.5
DUPLEXCHG
Duplex Change Status
1 = A Duplex Change has occurred since last
reading this register.
0 = A Duplex Change has not occurred since last
reading this register.
RO/SC
0
19.4
LINKCHG
Link Status Change Status
1 = A Link Change has occurred since last reading
this register.
0 = A Link Change has not occurred since last
reading this register.
RO/SC
0
19.3
Reserved
Ignore.
RO
0
19.2
MDINT
1 = MII interrupt pending.
0 = No MII interrupt pending.
RO
19.1
Reserved
Ignore.
RO
N/A
19.0
Reserved
Ignore
RO
0
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
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