參數(shù)資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁數(shù): 22/90頁
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
22
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
3.2
Network Media / Protocol Support
The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or
100 Mbps Ethernet over fiber media (100BASE-FX).
3.2.1
10/100 Network Interface
The network interface port consists of five external pins (two differential signal pairs and a signal
detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. Refer to
Figure 3 on page
13
for specific pin assignments.
The LXT971A output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the LXT971A generates 802.3-compliant link pulses or idle code.
Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending
on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine
the speed of this interface.
3.2.1.1
Twisted-Pair Interface
The LXT971A supports either 100BASE-TX or 10BASE-T connections over 100
,
Category
5,
Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT971A continuously
transmits and receives MLT3 symbols. When not transmitting data, the LXT971A generates
“IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link
up.
Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete
this interface. On the transmit side, the LXT971A has an active internal termination and does not
require external termination resistors. Intel's patented waveshaping technology shapes the outgoing
signal to help reduce the need for external EMI filters. Four slew rate settings (refer to
Table 4 on
page 18
) allow the designer to match the output waveform to the magnetic characteristics. On the
receive side, the internal impedance is high enough that it has no practical effect on the external
termination circuit.
3.2.1.2
Fiber Interface
The LXT971A fiber port is designed to interface with common industry-standard fiber modules. It
incorporates a Low Voltage PECL interface that complies with the ANSI X3.166 standard for
seamless integration.
Fiber mode is selected through Register bit 16.0 by the following two methods:
1. Drive the SD input to a value greater than 600 mV during power-up and reset states (all
LVPECL signaling levels from a fiber transceiver are acceptable).
2. Configure Register bit 16.0 = 1 through the MDIO interface.
相關(guān)PDF資料
PDF描述
LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972ALC 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
LXT972M Single-Port 10/100 Mbps PHY Transceiver
LXT9763 Fast Ethernet 10/100 Hex Transceiver with Full MII
LXT9763HC LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT971ABC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC
LXT971ABE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver
LXT971ALC 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP
LXT971ALE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver
LXT971LC 制造商:Intel 功能描述: