參數(shù)資料
型號(hào)： LXT971A
廠商： Intel Corp.
英文描述： 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述： 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁(yè)數(shù)： 26/90頁(yè)
文件大小： 568K
代理商： LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
26
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
3.3
Operating Requirements
3.3.1
Power Requirements
The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or
+3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the
other side of the MII interface. Refer to
Table 20 on page 57
for MII I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible.
3.3.2
Clock Requirements
3.3.2.1
External Crystal/Oscillator
The LXT971A requires a reference clock input that is used to generate transmit signals and recover
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to
Table 21 on page 57
for clock timing
requirements.
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to
Table 38 on page 69
for details.
3.4
Initialization
When the LXT971A is first powered on, reset, or encounters a link failure state, it checks the
MDIO register configuration bits to determine the line speed and operating conditions to use for
the network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in
Figure 7
.
3.4.1
MDIO Control Mode
In the MDIO Control mode, the LXT971A reads the Hardware Control Interface pins to set the
initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.
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