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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 71/90頁 |
| 文件大小： | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
71
6.0
Register Definitions
The LXT971A register set includes multiple 16-bit registers.
Table 41
presents a complete register
listing.
Table 42
is a complete memory map of all registers and
Tables 43
through
58
provide
individual register definitions.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique chip
functions.
Table 41. Register Set
Address
Register Name
Bit Assignments
0
Control Register
Refer to
Table 43 on page 74
1
Status Register #1
Refer to
Table 44 on page 75
2
PHY Identification Register 1
Refer to
Table 45 on page 76
3
PHY Identification Register 2
Refer to
Table 46 on page 76
4
Auto-Negotiation Advertisement Register
Refer to
Table 47 on page 77
5
Auto-Negotiation Link Partner Base Page Ability Register
Refer to
Table 48 on page 78
6
Auto-Negotiation Expansion Register
Refer to
Table 49 on page 79
7
Auto-Negotiation Next Page Transmit Register
Refer to
Table 50 on page 79
8
Auto-Negotiation Link Partner Received Next Page Register
Refer to
Table 51 on page 80
9
1000BASE-T/100BASE-T2 Control Register
Not Implemented
10
1000BASE-T/100BASE-T2 Status Register
Not Implemented
15
Extended Status Register
Not Implemented
16
Port Configuration Register
Refer to
Table 52 on page 81
17
Status Register #2
Refer to
Table 53 on page 82
18
Interrupt Enable Register
Refer to
Table 54 on page 83
19
Interrupt Status Register
Refer to
Table 55 on page 84
20
LED Configuration Register
Refer to
Table 56 on page 85
21-25
Reserved
–
26
Digital Config Register
Refer to
Table 57 on page 86
27-29
Reserved
–
30
Transmit Control Register
Refer to
Table 58 on page 87
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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