參數(shù)資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁數(shù): 37/90頁
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
37
As shown in
Figure 14 on page 36
, the MAC starts each transmission with a preamble pattern. As
soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT971A transmits the End-of- Stream Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in
Table 11 on page 40
.
Figure 16
shows normal reception with no errors. When the LXT971A receives invalid symbols
from the line, it asserts RX_ER as shown in
Figure 17
.
Figure 15. 100BASE-TX Data Path
S0
S1
S2
S3
S4
Parallel
to
Serial
Serial
to
Parallel
MLT3
0
+1
-1
0
0
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow
S0
S1
S2
S3
S4
Standard Data Flow
D0
D1
D2
D3
Parallel
to
Serial
Serial
to
Parallel
D0
D1
D2
D3
4B/5B
S0
S1
S2
S3
S4
MLT3
0
+1
-1
0
0
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scramble
De-
Scramble
Figure 16. 100BASE-TX Reception with No Errors
Figure 17. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
RXD<3:0>
RX_ER
preamble
SFD SFD
DA
DA
DA
DA
CRC
CRC
CRC
CRC
RX_CLK
RX_DV
RXD<3:0>
RX_ER
preamble
SFD SFD
DA
DA
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
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