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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 23/90頁 |
| 文件大小： | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
23
3.2.1.3
Fault Detection and Reporting
The LXT971A supports two fault detection and reporting mechanisms. “Remote Fault” refers to a
MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is
used only during auto-negotiation, and is applicable only to twisted-pair links. “Far-End Fault” is
an optional PMA-layer function that may be embedded within PHY devices. The LXT971A
supports both functions (see
Section 3.2.1.3.1
and
Section 3.2.1.3.2
).
3.2.1.3.1
Remote Fault
Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault
indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the
link partner that the link is down because the advertising device detected a fault.
When the LXT971A receives a Remote Fault indication from its partner during auto-negotiation it
does the following:
Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and
Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.
3.2.1.3.2
100BASE-FX Far-End Fault
The SD/TP pin monitors signal quality during normal operation in fiber mode. If the signal quality
degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via
the SD/TP pin. Loss of signal quality blocks any fiber data from being received and causes a link
loss.
If the LXT971A detects a signal fault condition, it can transmit the Far-End Fault Indication (FEFI)
over the fiber link. The FEFI consists of 84 consecutive ones followed by a single zero. This
pattern must be repeated at least three times. The LXT971A transmits the far-end fault code a
minimum of three times if all the following conditions are true:
Fiber mode is selected.
Fault Code transmission is enabled (Register bit 16.2 = 1).
Either Signal Detect indicates no signal or the receive PLL cannot lock.
Loopback is not enabled.
3.2.2
MII Data Interface
The LXT971A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT971A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically,
once the operating conditions of the network link have been determined. Refer to
“MII Operation”
on page 32
for additional details.
3.2.2.1
Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive
signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or
through a connector. The MII drive strength in the LXT971A can be increased by setting Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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