- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377799 > LXT971A (Intel Corp.) 3.3V Dual-Speed Fast Ethernet PHY Transceiver PDF資料下載
參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 33/90頁 |
| 文件大?。?/td> | 568K |
| 代理商： | LXT971A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
33
3.6.2
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
3.6.3
Receive Data Valid
The LXT971A asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble
of the data packet.
For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
3.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in half-duplex mode when a packet is transmitted.
Table 10
summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
3.6.5
Error Signals
When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts
RX_ER and drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT971A drives “H” symbols out on the TPFOP/N pins.
3.6.6
Collision
The LXT971A asserts its collision signal, asynchronously to any clock, whenever the line state is
half-duplex and the transmitter and receiver are active at the same time.
Table 10
summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。