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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 77/90頁 |
| 文件大?。?/td> | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
77
Table 47. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type
1
Default
4.15
Next Page
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
R/W
0
4.14
Reserved
Ignore.
RO
0
4.13
Remote Fault
1 = Remote fault.
0 = No remote fault.
R/W
0
4.12
Reserved
Ignore.
R/W
0
4.11
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
R/W
0
4.10
Pause
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
R/W
Note 2
4.9
100BASE-T4
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT971A does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-
negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver could be switched in
if this capability is desired.)
R/W
0
4.8
100BASE-TX
full-duplex
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.
R/W
Note 3
4.7
100BASE-TX
1 = Port is 100BASE-TX capable.
0 = Port is not 100BASE-TX capable.
R/W
Note 3
4.6
10BASE-T
full-duplex
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
R/W
Note 3
4.5
10BASE-T
1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.
R/W
Note 3
4.4:0
Selector Field,
S<4:0>
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future auto-negotiation
development.
<11111> = Reserved for future auto-negotiation
development.
Unspecified or reserved combinations should not be
transmitted.
R/W
00001
1. R/W = Read/Write
RO = Read Only
2. The default setting of Register bit 4.10 (PAUSE) is determined by pin 33/H8 at reset.
3. Default values of Register bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFG
n
pins at reset. Refer to
Table 9
for details.
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|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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