參數(shù)資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁數(shù): 28/90頁
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
28
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
3.4.3
Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
The LXT971A network port and clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Figure 7. Initialization Sequence
MDDIS Voltage
Level
High
Low
MDIO Control
Mode
Hardware Control
Mode
Disable MDIO Read and
Write Operations
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
MDIO Controlled Operation
(MDIO Writes Enabled)
Power-up or Reset
Initialize MDIO Registers
Read H/W Control
Interface
Software
Reset
Yes
No
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