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參數(shù)資料
| 型號： | LXT971A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| 中文描述： | 3.3雙速快速以太網(wǎng)物理層收發(fā)器 |
| 文件頁數(shù)： | 29/90頁 |
| 文件大?。?/td> | 568K |
| 代理商： | LXT971A |
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
29
3.4.3.2
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register (refer to
Table 43 on page 74
). During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
3.4.3.3
Sleep Mode
The LXT971A supports a power-saving sleep mode. Sleep mode is enabled when SLEEP is
asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by Register bit
16.6 when in managed mode as shown in
Table 4 on page 18
. The LXT971A enters into sleep
mode when SLEEP is enabled and no energy is detected on the twisted-pair input for 1-3 seconds
(the time is controlled by Register bits 16.4:3 in the Configuration Register, with a default of 3.04
seconds).
During this mode, the LXT971A still responds to management transactions (MDC/MDIO). In this
mode the power consumption is minimized, and the supply current is reduced below the maximum
value given in
Table 18 on page 56
. If the LXT971A detects activity on the twisted-pair inputs, it
comes out of the sleep state and check for link. If no link is detected in 1-3 seconds
(programmable) it reverts back to the low power sleep state.
Note:
Sleep Mode is not functional in fiber network applications.
3.4.4
Reset
The LXT971A provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, auto-negotiation and speed configuration settings are read in from pins (refer to
Table 9 on
page 30
for pin settings and to
Table 43 on page 74
for register bit definitions).
During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset is not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972A | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971ABC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| LXT971ABE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ALC | 制造商:Intel 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Intellon Corporation 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971ALE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971LC | 制造商:Intel 功能描述: |
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