參數(shù)資料
型號: LXT971A
廠商: Intel Corp.
英文描述: 3.3V Dual-Speed Fast Ethernet PHY Transceiver
中文描述: 3.3雙速快速以太網(wǎng)物理層收發(fā)器
文件頁數(shù): 70/90頁
文件大?。?/td> 568K
代理商: LXT971A
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
70
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 40. Power-Up Timing
Table 39. Power-Up Timing Parameters
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
Voltage threshold
v1
2.9
V
Power Up delay
2
t1
300
μ
s
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -
the PHY comes out of reset after a delay of No MORE Than 300
μ
s. System designers should consider this
as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300
μ
s before
accessing the MDIO port.
Figure 41. RESET Pulse Width and Recovery Timing
Table 40. RESET Pulse Width and Recovery Timing Parameters
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
RESET pulse width
t1
10
ns
RESET recovery delay
2
t2
300
μ
s
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance - the PHY comes out of reset after a delay of No MORE Than 300
μ
s. System designers
should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS
Than 300
μ
s before accessing the MDIO port.
t1
VCC
MDIO,etc
v1
t2
RESET
MDIO,etc
t1
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