- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369945 > P8XC591 (NXP Semiconductors N.V.) HiRel FPGA, Low-Power 1.0?? CMOS Technology PDF資料下載
參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 100/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)當(dāng)前第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
2000 Jul 26
100
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.3
Software Examples of SIO1 Service Routines
This section consists of a software example for:
Initialization of SIO1 after a RESET
Entering the SIO1 interrupt routine
The 26 state service routines for the
– Master transmitter mode
– Master receiver mode
– Slave receiver mode
– Slave transmitter mode
15.3.1
I
NITIALIZATION
In the initialization routine, SIO1 is enabled for both master
and slave modes. For each mode, a number of bytes of
internal data RAM are allocated to the SIO to act as either
a transmission or reception buffer. In this example, 8 bytes
of internal data RAM are reserved for different purposes.
The data memory map is shown in Figure 44. The
initialization routine performs the following functions:
S1ADR is loaded with the parts own slave address and
the general call bit (GC)
P1.6 and P1.7 bit latches are loaded with logic 1s
RAM location HADD is loaded with the high-order
address byte of the service routines
The SIO1 interrupt enable and interrupt priority bits are
set
The slave mode is enabled by simultaneously setting
the ENS1 and AA bits in S1CON and the serial clock
frequency (for master modes) is defined by loading CR0
and CR1 in S1CON. The master routines must be
started in the main program.
The SIO1 hardware now begins checking the I
2
C bus for
its own slave address and general call. If the general call
or the own slave address is detected, an interrupt is
requested and S1STA is loaded with the appropriate state
information. The following text describes a fast method of
branching to the appropriate service routine.
15.3.2
SIO1 I
NTERRUPT
R
OUTINE
When the SIO1 interrupt is entered, the PSW is first
pushed on the stack. Then S1STA and HADD (loaded with
the high-order address byte of the 26 service routines by
the initialization routine) are pushed on to the stack.
S1STA contains a status code which is the lower byte of
one of the 26 service routines. The next instruction is RET,
which is the return from subroutine instruction. When this
instruction is executed, the high and low order address
bytes are popped from stack and loaded into the program
counter.
The next instruction to be executed is the first instruction
of the state service routine. Seven bytes of program code
(which execute in eight machine cycles) are required to
branch to one of the 26 state service routines.
SI
PUSH
PSW
Save PSW
PUSH
S1STA
Push status code (low order
address byte)
PUSH
HADD
Push high order address byte
RET
Jump to state service routine
The state service routines are located in a 256-byte page
of program memory. The location of this page is defined in
the initialization routine. The page can be located
anywhere in program memory by loading data RAM
register HADD with the page number. Page 01 is chosen
in this example, and the service routines are located
between addresses 0100H and 01FFH.
15.3.3
T
HE
S
TATE
S
ERVICE
R
OUTINE
The state service routines are located 8 bytes from each
other. Eight bytes of code are sufficient for most of the
service routines. A few of the routines require more than 8
bytes and have to jump to other locations to obtain more
bytes of code. Each state routine is part of the SIO1
interrupt routine and handles one of the 26 states. It ends
with a RETI instruction which causes a return to the main
program.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201 | 16-bit microcontroller |
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P8XC592 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCE598 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCL580HFH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8XCL580HFT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。