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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 13/160頁 |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
13
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
7.1
Program Memory
The P8xC591 contains 16 Kbytes of on-chip Program
Memory which can be extended to 64 Kbytes with external
memories. When EA pin is held HIGH, the P8xC591
fetches instructions from internal ROM unless the address
exceeds 3FFFh. Locations 4000h to FFFFh are fetched
from external Program Memory. When the EA pin is held
LOW, all instruction fetches are from external memory.
The EA pin is latched during reset and is “don’t care” after
reset.
Both, for the ROM and EPROM version of the P8xC591,
precautions are implemented to protect the device against
illegal Program Memory code reading.
7.2
Addressing
The P8xC591 has five methods for addressing the
Program and Data memory:
Register
Direct
Register-Indirect
Immediate
Base-Register plus Index-Register-Indirect.
For more details about Addressing modes please refer to
Section 22.1 “Addressing Modes”.
7.3
Expanded Data RAM addressing
The P8xC591 has internal data memory that is mapped
into four separate segments: the lower 128 bytes of RAM,
upper 128 bytes of RAM, 128 bytes Special Function
Register (SFR), and 256 bytes Auxiliary RAM (AUX-RAM)
as shown in Figure 5.
The four segments are:
1.
The Lower 128 bytes of RAM (addresses 00H to 7FH)
are directly and indirectly addressable (see Fig.6).
2.
The Upper 128 bytes of RAM (addresses 80H to FFH)
are indirectly addressable.
3.
The Special Function Registers, SFRs, (addresses
80H to FFH) are directly addressable only. All these
SFRs are described in Table 4.
4.
The 256-bytes AUX-RAM (00H - FFH) are indirectly
accessed by move external instruction, MOVX, and
within the EXTRAM bit cleared, see Table 3.
The Lower 128 bytes can be accessed by either direct or
indirect addressing. The Upper 128 bytes can be
accessed by indirect addressing only. The Upper 128
bytes occupy the same address space as the SFR. That
means they have the same address, but are physically
separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to the
upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction. Instructions that
use direct addressing access SFR space.
For example:
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2).
Instructions that use indirect addressing access the Upper
128 bytes of data RAM.
For example:
MOV @ R0,#data
where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
The AUX-RAM can be accessed by indirect addressing,
with EXTRAM bit cleared and MOVX instructions. This
part of memory is physically located on-chip, logically
occupies the first 256-bytes of external data memory.
With EXTRAM = 0, the AUX-RAM is indirectly addressed,
using the MOVX instruction in combination with any of the
registers R0, R1 of the selected bank or DPTR. An access
to AUX-RAM will not affect ports P0, P3.6 (WR#) and P3.7
(RD#). P2 SFR is output during external addressing. For
example, with EXTRAM = 0,
MOV @ R0,#data
where R0 contains 0A0h, access the AUX-RAM at
address 0A0H rather than external memory. An access to
external data memory locations higher than FFH (i.e.,
0100H to FFFFH) will be performed with the MOVX DPTR
instructions in the same way as in the standard 80C51, so
with P0 and P2 as data/address bus, and P3.6 and P3.7
as write and read timing signals. Refer to Table 4.
With EXTRAM = 1, MOVX @ Ri and MOVX @ DPTR will
be similar to the standard 80C51. MOVX @ Ri will provide
an 8-bit address multiplexed with data on Port 0 and any
output port pins can be used to output higher order
address bits. This is to provide the external paging
capability. MOVX @ DPTR will generate a 16-bit address.
Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order
eightaddressbits(DPL)withdata.MOVX@RiandMOVX
@ DPTR will generate either read or write signals on P3.6
(#WR) and P3.7 (#RD).
The stack pointer (SP) may be located anywhere in the
256 bytes RAM (lower and upper RAM) internal data
memory. The stack cannot be located in the AUX-RAM.
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