- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369945 > P8XC591 (NXP Semiconductors N.V.) HiRel FPGA, Low-Power 1.0?? CMOS Technology PDF資料下載
參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 67/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)當(dāng)前第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
2000 Jul 26
67
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the left most position in the
shift register (which in Mode 1 is a 9-bit register), it flags
the RX Control block to do one last shift, load S0BUF and
RB8, and set RI. The signal to load S0BUF and RB8, and
to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is
generated:
1.
RI = 0, and
2.
Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into S0BUF, and
RI is activated. At this time, whether the above conditions
are met or not, the unit goes back to looking for a 1-to-0
transition in RxD.
More About Modes 2 and 3
Eleven bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9
th
data bit, and a stop bit (1). On transmit,
the 9
th
data bit (TB8) can be assigned the values of 0 or 1.
On receive, the 9
the
data bit goes into RB8 in SCON. The
baud rate is programmable to either
1
16
or
1
32
the
oscillator frequency in Mode 2. Mode 3 may have a
variable baud rate generated from Timer 1.
Figure 25 show a functional diagram of the serial port in
Modes 2 and 3. The receive portion is exactly the same as
in Mode 1. The transmit portion differs from Mode 1 only in
the 9
th
bit of the transmit shift register.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signalalsoloadsTB8intothe9
th
bitpositionofthetransmit
shift register and flags the TX Control unit that a
transmission is requested. Transmission commences at
S1P1ofthemachinecyclefollowingthenextrolloverinthe
divide-by-16 counter. (Thus, the bit times are
synchronized to the divide-by-16 counter, not to the “write
to SUB” signal).
The transmission begins with activation of SEND, which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time
after that. The first shift clocks a 1 (the stop bit) into the 9
th
bit position of the shift register. Thereafter, only zeros are
clocked in. Thus, as data bit shift out to the right, zeros are
clocked in from the left. When TB8 is at the output position
of the shift register, then the stop bit is just to the left of
TB8, and all positions to the left of that contain zeros.
This condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at the
11
th
divide-by-16 rollover after “write to SUBF”.
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxD is sampled at a rate of 16 times
whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written to the input shift
register.
At the 7
th
, 8
th
, and 9
th
counter states of each bit time, the
bit detector samples the value of R-D. The value accepted
is the value that was seen in at least 2 of the 3 samples. If
the value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking
for another 1-to-0 transition. If the start bit proves valid, it
is shifted into the input shift register, and reception of the
rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the left most position in the
shift register (which in Modes 2 and 3 is a 9-bit register), it
flags the RX Control block to do one last shift, load S0BUF
and RB8, and set RI.
The signal to load S0BUF and RB8, and to set RI, will be
generated if, and only if, the following conditions are met
at the time the final shift pulse is generated.
1.
RI = 0, and
2.
Either SM2 = 0, or the received 9
th
data bit = 1.
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met, the received 9
th
data bit goes into RB8, and the first 8
data bits go into S0BUF. One bit time later, whether the
above conditions were met or not, the unit goes back to
looking for a 1-to-0 transition at the RxD input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201 | 16-bit microcontroller |
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P8XC592 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCE598 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCL580HFH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8XCL580HFT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。