參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 147/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
147
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Note
1.
Parts a guaranteed to operate down to 0 Hz.
Table 112
I
2
C-bus interface timing
All values referred to V
IH(min)
and V
IL(max)
levels; see Fig.61.
Notes
1.
2.
3.
At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
Spikes on the SDA and SCL lines with a duration of less than 3 t
CLK
will be filtered out. Maximum capacitance on
bus-lines SDA and SCL = 400 pF.
t
CLK
= 1/f
CLK
= one oscillator clock period at pin XTAL1. For 83 ns < t
CLK
< 285 ns (12 MHz > f
CLK
> 3.5 MHz) the
SI01 interface meets the I
2
C-bus specification for bit-rates up to 100 kbit/s.
These values are guaranteed but not 100% production tested.
4.
5.
UART Timing - Shift Register Mode;
see Fig.59
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
serial port clock cycle time
output data setup to clock rising edge
output data hold after clock rising edge
input data hold after clock rising edge
clock rising edge to input data valid
500
284
53
0
6 t
CLK
ns
ns
ns
ns
ns
5 t
CLK
133
t
CLK
30
0
284
5 t
CLK
133
SYMBOL
PARAMETER
I
2
C-BUS
INPUT
≥
7 t
CLK
≥
8 t
CLK
≥
7 t
CLK
≤
1
μ
s
≤
0.3
μ
s
≥
250 ns
≥
250 ns
≥
250 ns
≥
0 ns
≥
7 t
CLK
≥
7 t
CLK
≥
7 t
CLK
≤
1
μ
s
≤
0.3
μ
s
OUTPUT
> 4.0
μ
s
(1)
> 4.7
μ
s
(1)
> 4.0
μ
s
(1)
(2)
< 3.0
μ
s
(3)
> 10 t
CLK
t
RD
> 1
μ
s
(1)
> 4 t
CLK
> 4 t
CLK
t
FC
> 4.7
μ
s
(1)
> 4.0
μ
s
(1)
> 4.7
μ
s
(1)
(2)
< 0.3
μ
s
(3)
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
START condition hold time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of SCL signals
fall time of SCL signals
data set-up time
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
data hold time
set-up time for a repeated START condition
set-up time for STOP condition
bus free time between
rise time of SDA signals
fall time of SDA signals
SYMBOL
PARAMETER
12 MHz CLOCK
VARIABLE CLOCK
UNIT
MIN.
MAX.
MIN.
MAX.
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