- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369945 > P8XC591 (NXP Semiconductors N.V.) HiRel FPGA, Low-Power 1.0?? CMOS Technology PDF資料下載
參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 117/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁當(dāng)前第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁
2000 Jul 26
117
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
16.1.4
C
APTURE
L
OGIC
The four 16-bit capture registers that Timer T2 is
connected to are: CT0, CT1, CT2, and CT3. These
registers are loaded with the contents of Timer T2, and an
interrupt is requested upon receipt of the input signals
CT0l, CT1I, CT2l, or CT3l. These input signals are shared
with port 1. The four interrupt flags are in the Timer T2
interrupt register (TM2lR special function register). If the
capture facility is not required, these inputs can be
regarded as additional external interrupt inputs (INT2 to
INT5).
Using the capture control register CTCON (see
Section 16.1.4.1), these inputs may capture on a rising
edge, a falling edge, or on either a rising or falling edge.
The inputs are sampled during S1P1 of each cycle. When
a selected edge is detected, the contents of Timer T2 are
captured at the end of the cycle.
16.1.4.1
Table 72
Capture Control Register (address EBH)
Capture Control Register (CTCON)
Table 73
Description of CTCON bits
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Capture Register 3 triggered by a falling edge on CT3l.
Capture Register 3 triggered by a rising edge on CT3l.
Capture Register 2 triggered by a falling edge on CT2l.
Capture Register 2 triggered by a rising edge on CT2l.
Capture Register 1 triggered by a falling edge on CT1l.
Capture Register 1 triggered by a rising edge on CT1l.
Capture Register 0 triggered by a falling edge on CT0l.
Capture Register 0 triggered by a rising edge on CT0l.
16.1.5
M
EASURING
T
IME
I
NTERVALS
U
SING
R
EGISTERS
When a recurring external event is represented in the form
of rising or falling edges on one of the four capture pins,
the time between two events can be measured using
Timer T2 and a capture register. When an event occurs,
the contents of Timer T2 are copied into the relevant
capture register and an interrupt request is generated. The
interrupt service routine may then compute the interval
time if it knows the previous contents of Timer T2 when the
last event occurred. With a 6 MHz oscillator, Timer T2 can
be programmed to overflow every 524 ms. When event
interval times are shorter than this, computing the interval
time is simple, and the interrupt service routine is short.
For longer interval times, the Timer T2 extension routine
may be used.
16.1.6
C
OMPARE
L
OGIC
Each time Timer T2 is incremented, the contents of the
three 16-bit compare registers CM0, CM1, and CM2 are
compared with the new counter value of Timer T2. When
amatchisfound, thecorresponding interrupt flagin TM2lR
is set at the end of the following cycle. When a match with
CM0 occurs, the controller sets bits 0-3 of port 3 if the
corresponding bits of the set enable register STE are at
logic 1 (see Section 16.1.6.2).
When a match with CM1 occurs, the controller resets bits
0-3 of port 3 if the corresponding bits of the reset/enable
register RTE are at logic 1 (see Section 16.1.6.1). If RTE
is “0”, then P3.n is not affected by a match between CM1
or CM2 and Timer 2.
Thus, if the current operation is “set,” the next operation
will be “reset” even if the port latch is reset by software
before the “reset” operation occurs. CM0, CM1, and CM2
are reset by the RST signal.
The modified port latch information appears at the port pin
during S5P1 of the cycle following the cycle in which a
match occurred. If the port is modified by software, the
outputs change during S1P1 of the following cycle. Each
port 3 bit (0-3) can be set or reset by software at any time.
A hardware modification resulting from a comparator
match takes precedence over a software modification in
the same cycle. When the comparator results require a
“set” and a “reset” at the same time, the port latch will be
reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201 | 16-bit microcontroller |
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P8XC592 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCE598 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCL580HFH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8XCL580HFT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。