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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 76/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
76
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2
SIO1 Implementation and Operation
Figure 32 shows how the on-chip I
2
C bus interface is
implemented, and the following text describes the
individual blocks.
15.2.1
I
NPUT
F
ILTERS AND
O
UTPUT
S
TAGES
The input filters have I
2
C compatible input levels. If the
input voltage is less than 1.5 V, the input logic level is
interpreted as 0; if the input voltage is greater than 3.0 V,
the input logic level is interpreted as 1. Input signals are
synchronized with the internal clock (f
CLK
/4), and spikes
shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that
can sink 3 mA at V
OUT
< 0.4 V. These open drain outputs
do have clamping diodes to V
DD
. Thus, precautions have
tobeconsidered,ifapowered-down8xC591ononeboard
clamps the I
2
C bus externally.
15.2.2
A
DDRESS
R
EGISTER
, S1ADR
This 8-bit special function register may be loaded with the
7-bit slave address (7 most significant bits) to which SIO1
will respond when programmed as a slave transmitter or
receiver. The LSB (GC) is used to enable general call
address (00H) recognition.
15.2.3
C
OMPARATOR
The comparator compares the received 7-bit slave
address with its own slave address (7 most significant bits
in S1ADR). It also compares the first received 8-bit byte
with the general call address (00H). If an equality is found,
the appropriate status bits are set and an interrupt is
requested.
15.2.4
S
HIFT
R
EGISTER
, S1DAT
This 8-bit special function register contains a byte of serial
data to be transmitted or a byte which has just been
received. Data in S1DAT is always shifted from right to left;
the first bit to be transmitted is the MSB (bit 7) and, after a
byte has been received, the first bit of received data is
located at the MSB of S1DAT. While data is being shifted
out, data on the bus is simultaneously being shifted in;
S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from
master transmitter to slave receiver is made with the
correct data in S1DAT.
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