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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 144/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
144
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Notes to the DC characteristics
1.
8-bit mode
2.
See Figures 62 through 64 for I
DD
test conditions.
3.
The operating supply current is measured with all output pins disconnected; XTAL1 driven with
t
r
= t
f
= 10 ns; V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; EA = Port 0 = V
DD
; = RST = V
SS
.
4.
The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10 ns;
V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected; Port 0 = RST = V
DD
; EA = V
SS
.
5.
The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
RST = Port 0 = V
DD
; EA = XTAL1 = V
SS
.
6.
The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so an input voltage below 1.5 V will
be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
7.
Pins of Port 1 (except P1.6, P1.7), 2 and 3 source a transition current when they are being externally driven from
HIGH to LOW. The transition current reaches its maximum value when V
IN
is approximately 2 V.
8.
Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
of ALE and
Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these
pins make HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the
noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt
Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that
no single outputs sinks more than 5 mA and no more than two outputs exceed in the test conditions.
9.
Capacitive loading on Ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9 V
DD
specification when the address bits are stabilizing.
10. Conditions: AV
SS
= 0 V; V
DD
= 5.0 V. Measurement by continuous conversion of AV
IN
=
20 mV to 5.12 V in steps
of 0.5 mV, derivating parameters from collected conversion results of ADC. AV
REF+
(P8xC591) = 4.977 V, ADC is
monotonic with not missing codes.
11. The differential non-linearity (D
Le
) is the difference between the actual step width and the ideal step width (see
Fig.54).
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (I
Le
) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error (see Fig.54).
14. The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve (after
removing gain error), and a straight line which fits the ideal transfer curve (see Fig.54).
15. The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after
removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point
on the transfer curve (see Fig.54).
16. The absolute voltage error (A
e
) is the maximum difference between the centre of the steps of the actual transfer curve
of the non-calibrated ADC and the ideal transfer curve.
17. This should be considered when both analog and digital signals are simultaneously input to Port 1.
18. The parameter is guaranteed by design and characterized, but is not production tested.
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