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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 21/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
21
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
8
I/O FACILITIES
The P8xC591 consists of 32 I/O Port lines with partly
multiple functions. The I/O’s are held HIGH during reset
(asynchronous, before oscillator is running).
Ports 0, 1, 2 and 3 perform the following alternative
functions:
Port 0 is the same as in the 80C51. After reset the Port
Special Function Register is set to ‘FFh’ as known
from other 80C51 derivatives. Port 0 also provides
the multiplexed low-order address and data bus
used for expanding the P8xC591 with standard
memories and peripherals.
Port 1 supports several alternative functionalities. For this
reason it has different I/O stages. Note, port P1.0
and P1.1 are Driven-High and P1.2 to P1.7 are
High-Impedance (Tri-state) after reset.
Port 2 is the same as in the 80C51. After reset the Port
Special Function Register is set to ‘FFh’ as known
from other 80C51 derivatives. Port 2 also provides
the high-order address bus when the P8xC591 is
expanded with external Program Memory and/or
external Data Memory.
Port 3 is the same as in the 80C51. During reset the Port
3SpecialFunctionRegisterissetto‘FFh’asknown
from other 80C51 derivatives.
9
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier. The pins can be configured for
use as an on-chip oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1
should be driven while XTAL2 is left unconnected. There
are no requirements on the duty cycle of the external clock
signal. However, minimum and maximum high and low
times specified in the data sheet must be observed.
10 RESET
A reset is accomplished by holding the RST pin LOW for
at least two machine cycles (12 oscillator periods), while
the oscillator is running. To insure a good power-on reset,
theRSTpinmustbelowlongenoughtoallowtheoscillator
time to start up (normally a few milliseconds) plus two
machine cycles.
The RST line can also be pulled LOW internally by a
pull-down transistor activated by the watchdog timer T3.
ThelengthoftheoutputpulsefromT3is3machinecycles.
A pulse of such short duration is necessary in order to
recover from a processor or system fault as fast as
possible.
Note that the short reset pulse from Timer T3 cannot
discharge the power-on reset capacitor (see Figure 8).
Consequently,whenthewatchdogtimerisalsousedtoset
externaldevices,thiscapacitorarrangementshouldnotbe
connected to the RST pin, and a different circuit should be
used to perform the power-on reset operation. A timer T3
overflow, if enabled, will force a reset condition to the
P8xC591 by an internal connection, whether the output
RST is pulled-up HIGH or not.
A reset may be performed in software by setting the
software reset bit, SRST (AUXR1.5).
This device also has a Power-on Detect Reset circuit as
V
CC
transitions from V
CC
past V
RST
.
Fig.8 On-Chip Reset Configuration.
handbook, halfpage
MHI008
SCHMITT
TRIGGER
RESET
CIRCUITRY
RST
overflow
timer T3
on-chip
resistor
VDD
Fig.9 Power-on Reset.
handbook, halfpage
MHI009
RST
RRST
2.2
μ
F
P8xC591
VDD
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