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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 71/160頁 |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
71
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
14.5
Enhanced UART
The UART operates in all of the usual modes that are
described in the Section of Standard Serial Interface,
80C51-Based 8-Bit Microcontrollers. In addition the UART
can perform framing error detect by looking for missing
stop bits, and automatic address recognition. The UART
also fully supports multiprocessor communication as does
the standard 80C51 UART.
When used for framing error detect the UART looks for
missing stop bits in the communication. A missing bit will
set the FE bit in the S0CON register. The FE bit shares the
S0CON.7 bit with SM0 and the function of S0CON.7 is
determined by PCON.6 (SMOD0) see Table 50. If SMOD0
is set then S0CON.7 functions as FE. S0CON.7 functions
as SM0 when SMOD0 is cleared. When as FE S0CON.7
can only be cleared by software. Refer to Figure 25.
14.5.1
A
UTOMATIC
A
DDRESS
R
ECOGNITION
Automatic Address Recognition is a feature which allows
the UART to recognize certain addresses in the serial bit
stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by
eliminating the need for the software to examine every
serialaddress whichpasses bythe serialport.This feature
is enabled by setting the SM2 bit in S0CON. In the 9 bit
UART modes, mode 2 and mode 3, the Receive Interrupt
flag (RI) will be automatically set when the received byte
contains either the “Given” address or the “Broadcast”
address. The 9 bit mode requires that the 9th information
bit is a 1 to indicate that the received information is an
address and not data. Automatic address recognition is
shown in Figure 29.
The 8 bit mode is called Mode 1. In this mode the RI flag
will be set if SM2 is enabled and the information received
has a valid stop bit following the 8 address bits and the
information is either a Given or Broadcast address.
14.5.2
S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(S0CON)
Table 49
Serial Port Control Register (address 98H)
Table 50
Description of S0CON bits
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
SYMBOL
DESCRIPTION
7
FE
SM0
SM1
SM2
Framing Error bit.
This bit is set by the receiver when an invalid stop bit is detected. The FE
bit is not cleared by valid frames but should be cleared by software.
Serial Port Mode Bit 0,
(SMOD0 must = 0 to access bit SM0), see Table 46.
These bits are used to select the serial port mode; see Table 46.
Enables the Automatic Address Recognition
feature in Modes 2 and 3. If SM2 = 1, then RI
will not be set unless the received 9
th
data bit (RB8) is a logic 1, indicating an address, and the
received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1, then RI will not be
activated unless a valid stop bit was not received, and the received byte is a Given or
Broadcast Address. In Mode 0, SM2 should be a logic 0.
Enables serial reception.
Set by software to enable reception. Clear by software to disable
reception.
The 9
th
data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9
th
data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit
that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag
. Set by hardware at the end of the 8
th
bit time in Mode 0, or at the
beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by
software.
Receive Interrupt flag
. Set by hardware at the end of the 8
th
bit time in Mode 0, or halfway
through the stop bit time in the other modes, in any serial reception (except see SM2). Must
be cleared by software.
6
5
4
REN
3
2
TB8
RB8
1
TI
0
RI
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